When used to implement a sequential logic element, the three input signals from the connection mux go to the data (D), clock (CLK), and reset/set (nRST/nSET) inputs for the flip-flop or latch, with the output going back to the connection mux. This macro-cell has user-configurable initial state, clock polarity, reset/set polarity, output select, and output polarity parameters.

The operation of the D flip-flop/latch will follow the functional descriptions below:

• The clock polarity is configurable and can be set to non-inverted (CLK) or inverted (nCLK).

  • DFF with CLK: CLK is rising edge triggered, then Q = D; otherwise Q will not change.
  • DFF with nCLK: CLK is falling edge triggered, then Q = D; otherwise Q will not change.
  • Latch with CLK: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is High).

  • Latch with nCLK: when CLK is High, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK is Low).

• These DFF/Latches have an option for both an active-low and active-high reset/set:

  • nRST: If High, then the DFF/Latch is in normal operation. If Low, then Q is reset to 0.

  • RST: If Low, then the DFF/Latch is in normal operation. If High, then Q is reset to 0.

  • nSET: If High, then the DFF/Latch is in normal operation. If Low, then Q is set to 1.

  • SET: If Low, then the DFF/Latch is in normal operation. If High, then Q is set to 1.

• If reset/set is not desired, users may set the polarity to active-low and connect this input to V_CC or a constant High source.

• These DFF/Latches have the option to further isolate the output from the input with the use of a second DFF/Latch and sampling on the falling edge of CLK and enabling the "Dual Stage DFF" option.

• The output polarity is configurable and can be set to non-inverted (Q) or inverted (nQ).

Table 7-18 and Table 7-19 show the truth tables for the D flip-flop and D latch with an active-low reset/set, respectively.