In order for the McACMP macro-cell to be used in a TPLD design, the power up (PUP) port needs to be connected to a logic High signal. By connecting to signals coming from the connection mux, it is possible to have the McACMP always on, always off, or switched on dynamically based on a digital signal coming from the connection mux.

• PUP = 1 => McACMP is powered up.
• PUP = 0 => McACMP is powered down.

Upon power up, the output will remain static and then become valid t_start after the PUP signal goes high, during which time, ensure OSC1 is not powered down.

The McACMP macro-cell has a positive input signal that can be provided by a variety of external sources with a selectable gain stage before going into the analog comparator. The negative input signal can either come from the internal VREF or an external source, which is shared between all comparator channels. Each channel has the option to select up to four negative input points to compare against.

IN+ gain: The McACMP positive input can be provided by a variety of external sources, and can also have a selectable gain stage (1X, 0.5X, 0.33X, 0.25X) before connecting to the analog comparator.

IN- voltage range: 32 mV to 2.016 V through the internal VREF or up to 2.016 V external source.

The VREF selection per channel of the multi-channel sampling analog comparator may be updated in-system using the User Registers. For glitch-free measurements, it is recommended to disable/power down all analog comparators when changing the VREF. If the analog comparator is not disabled while the VREF selection is being updated, it may take up to 10µs for valid data to be output from the analog comparators.

Hysteresis: If the internal VREF is used, corresponding McACMP channels have four selectable hysteresis options 0 mV, 32 mV, 64 mV and 192 mV.

• 0 mV: will disable the input signal hysteresis.
• 64 mV: is a +32 mV and -32 mV hysteresis. For VREF = 1.024 V, the trigger points will be 1.056 V and 0.992 V.
• 128 mV: is a +64 mV and -64 mV hysteresis. For VREF = 1.024 V, the trigger points will be 1.088 V and 0.960 V.
• 192 mV: is a +96 mV and -96 mV hysteresis. For VREF = 1.024 V, the trigger points will be 1.120 V and 0.928 V.

If hysteresis is desired, the internal VREF must be used. Further, hysteresis values that would otherwise extend beyond the range of the VREF will be limited to the minimum and maximum values available in the device. For example, if IN- = 1.984 V and VHYS = ±64 mV, the lower trigger point will be 1.920 V and the upper trigger point will be 2.016 V.

When only one channel and one VREF is selected, the McACMP will disable the sampling engine and operate as a discrete analog comparator.

In multi-channel sampling mode, the TPLD2001 can be configured to sample up to 4 channels, each with its own selectable gain, voltage reference, and hysteresis (if the internal VREF is used). The sampling clock can be selected from the output of OSC0 or OSC1 with a given pre-divider and an additional divider at the McACMP. Other configurations that can be set are the output synchronicity, the trigger to begin a sample sequence, a sequence restart and output latch reset/clear input, and the option to select up to 2 VREFs per channel.

When sampling in multi-channel mode, the McACMP will sample the set channels in sequential order (channel 0 through channel n) and the edge of the clock on which samples are captured can be selected.

Clock: The McACMP sampling clock can be selected to be OSC1 / 20, OSC1 / 40, OSC0, or OSC0 / 2.

Enable trigger:

• Edge sensitive PUP mode: The McACMP will begin one sampling sequence when a rising edge is detected at the PUP input and then enter an idle state.

• Level sensitive PUP mode: The McACMP will begin the sampling sequence when a high signal is detected at the PUP input and continuously sample as long as PUP is high, and once PUP goes low, the McACMP will finish the sampling sequence before entering an idle state.

Output synchronicity:

• Simultaneous: Sampled outputs will be latched and then appear at their respective channel output after the last channel is sampled.

• Staggered: Sampled outputs will appear at their respective channel output as they are sampled.

Sampling edge select:

• Negative edge: samples are captured on the negative or falling edge of the clock.

• Positive edge: samples are captured on the positive or rising edge of the clock.

Sequence restart/output latch reset: while the McACMP is running, a restart/reset signal can be asserted to restart the sampling sequence from channel 0. Channels can also independently be selected to have the output latch data cleared when this signal is asserted.

There is also a data ready output that will assert a high signal for one clock of the base clock frequency once all channels configured have been sampled. For example, if the 1kHz (2kHz/2) sampling clock is selected, the data ready pulse width will be 500µs.

Figure 7-44 shows and example of a McACMP configured to sample channel 0 and channel 1 with 2 VREFs each and only channel 0 with the output latch reset enabled.