SCPS286 July   2025 TPLD2001

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Bus Timing Requirements
    9. 5.9 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.3.1 3-Bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-Bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-Bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.5.1 4-Bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing blocks
        1. 7.3.4.1 3-Bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Comparator Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Analog Comparators
        1. 7.3.11.1 Discrete Analog Comparator (ACMP)
        2. 7.3.11.2 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Analog Multiplexer (AMUX)
      15. 7.3.15 Oscillators
        1. 7.3.15.1 2kHz Fixed Frequency Oscillator
        2. 7.3.15.2 2MHz Fixed Frequency Oscillator
        3. 7.3.15.3 25MHz Fixed Frequency Oscillator
        4. 7.3.15.4 Oscillator Power Modes
      16. 7.3.16 Serial Communications
        1. 7.3.16.1 I2C Mode
        2. 7.3.16.2 SPI Mode
        3. 7.3.16.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP)
        3. 7.4.4.3 Intel HEX File Format
        4. 7.4.4.4 TPLD2001 Registers
          1. 7.4.4.4.1 TPLD2001_User Registers
          2. 7.4.4.4.2 TPLD2001_Cfg_0 Registers
          3. 7.4.4.4.3 TPLD2001_Cfg_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

7.3.1.3 Pull-Up or Pull-Down Resistors

All I/O pins have the option of user-selectable resistors that can be connected to the pin structure. The selectable values on these resistors are 10kΩ, 100kΩ and 1MΩ. The internal resistors can be configured as either pull-up or pull-down. When designing in InterConnect Studio, any pin left unused in a design are configured with a 1MΩ pull-down by default. Furthermore, following a power-on event, all ports are in a Hi-Z state until the power-on reset sequence has completed.

Table 7-1 Pin Configuration Options

GPIO

 IO selection OE IO options Resistor Resistor value (Ω)
IN0 Pin not used — — Pull Down 1 M
Digital input 0

Digital in without Schmitt trigger

Digital in with Schmitt trigger

Low voltage digital input

 Floating —
Pull Down

Pull Up

10 k

100 k

1 M
IO6, IO7 Pin not used — — Pull Down 1 M
Digital input 0

Digital in without Schmitt trigger

Digital in with Schmitt trigger

Low voltage digital input

 Floating —
Pull Down

Pull Up

10 k

100 k

1 M
Digital output 1 Push pull (1X, 2X)Open drain NMOS (1X, 4X) Floating —
Pull Down

Pull Up

10 k

100 k

1 M
IO1, IO2,

IO3, IO10, IO11, IO12, IO13, IO15, IO16, IO17

 Pin not used — — Pull Down 1 M
Digital input 0

Digital in without Schmitt trigger

Digital in with Schmitt trigger

Low voltage digital input

 Floating —
Pull Down

Pull Up

10 k

100 k

1 M
Digital output 1 Push pull (1X, 2X) Floating —

Open drain NMOS (1X, 2X)

3-state output (1X, 2X)

 Pull Down

Pull Up

10 k

100 k

1 M
Digital input/output 0

Digital in without Schmitt trigger

Digital in with Schmitt trigger

Low voltage digital input

 Floating —
Pull Down

Pull Up

10 k

100 k

1 M
1 Push pull (1X, 2X)

Open drain NMOS (1X, 2X)
Analog input/output — Analog input/output Floating —
Pull Down

Pull Up

10 k

100 k

1 M
IO5, IO8 Pin not used — — Pull Down 1 M
Digital input 0

Digital in without Schmitt trigger

Digital in with Schmitt trigger

Low voltage digital input

 Floating —
Pull Down

Pull Up

10 k

100 k

1 M
Digital output 1 Push pull (1X, 2X) Floating —

Open drain NMOS (1X, 2X)

 Pull Down

Pull Up

10 k

100 k

1 M
Digital input/output 0

Digital in without Schmitt trigger

Digital in with Schmitt trigger

Low voltage digital input

 Floating —
Pull Down

Pull Up

10 k

100 k

1 M
1 Push pull (1X, 2X)

Open drain NMOS (1X, 2X)
IO4, IO9, IO14 Pin not used — — Pull Down 1 M
Digital input 0

Digital in without Schmitt trigger

Digital in with Schmitt trigger

Low voltage digital input

 Floating —
Pull Down

Pull Up

10 k

100 k

1 M
Digital output 1 Push pull (1X, 2X) Floating —

Open drain NMOS (1X, 2X)

 Pull Down

Pull Up

10 k

100 k

1 M
Analog input/output — Analog input/output Floating —
Pull Down

Pull Up

10 k

100 k

1 M

Note:

When using an IO with output-enable (OE) controlled from the CMX, configured as a Digital output with 3-state output, it is recommended to configure the input mode to Digital in with Schmitt trigger.