SCPS286 July   2025 TPLD2001

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Bus Timing Requirements
    9. 5.9 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.3.1 3-Bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-Bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-Bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.5.1 4-Bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing blocks
        1. 7.3.4.1 3-Bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Comparator Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Analog Comparators
        1. 7.3.11.1 Discrete Analog Comparator (ACMP)
        2. 7.3.11.2 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Analog Multiplexer (AMUX)
      15. 7.3.15 Oscillators
        1. 7.3.15.1 2kHz Fixed Frequency Oscillator
        2. 7.3.15.2 2MHz Fixed Frequency Oscillator
        3. 7.3.15.3 25MHz Fixed Frequency Oscillator
        4. 7.3.15.4 Oscillator Power Modes
      16. 7.3.16 Serial Communications
        1. 7.3.16.1 I2C Mode
        2. 7.3.16.2 SPI Mode
        3. 7.3.16.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP)
        3. 7.4.4.3 Intel HEX File Format
        4. 7.4.4.4 TPLD2001 Registers
          1. 7.4.4.4.1 TPLD2001_User Registers
          2. 7.4.4.4.2 TPLD2001_Cfg_0 Registers
          3. 7.4.4.4.3 TPLD2001_Cfg_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

7.3.12 Voltage Reference (VREF)

The TPLD2001 has a voltage reference macro-cell to provide references to the analog comparators. This macro-cell provides a user selection of fixed voltage references from 32 mV to 2.016 V in 32 mV increments or an externally supplied voltage reference from the External VREF AIO can be provided. The External VREF option is shared between all comparators and all channels of the McACMP.

When operating on a VCC less than 2.3 V, the maximum VREF option is reduced to VCC - 0.3 V; thus, the maximum VREF when operating at 1.8 V supply is 1.504 V.

The VREF selection per discrete analog comparator or per channel of the multi-channel sampling analog comparator can be updated in-system using the User Registers. For glitch-free measurements, it is recommended to disable/power down all analog comparators when changing the VREF. If the analog comparator is not disabled while the VREF selection is being updated, it may take up to 10µs for valid data to be output from the analog comparators.

Table 7-23 VREF Selection Table

Bit Enumeration

VREF output
000000 32 mV
000001 64 mV
000010 96 mV
000011 128 mV
000100 160 mV
000101 192 mV
000110 224 mV
000111 256 mV
001000 288 mV
001001 320 mV
001010 352 mV
001011 384 mV
001100 416 mV
001101 448 mV
001110 480 mV
001111 512 mV
010000 544 mV
010001 576 mV
010010 608 mV
010011 640 mV
010100 672 mV
010101 704 mV
010110 736 mV
010111 768 mV
011000 800 mV
011001 832 mV
011010 864 mV
011011 896 mV
011100 928 mV
011101 960 mV
011110 992 mV
011111 1024 mV
100000 1056 mV
100001 1088 mV
100010 1120 mV
100011 1152 mV
100100 1184 mV
100101 1216 mV
100110 1248 mV
100111 1280 mV
101000 1312 mV
101001 1344 mV
101010 1376 mV
101011 1408 mV
101100 1440 mV
101101 1472 mV
101110 1504 mV
101111 1536 mV
110000 1568 mV
110001 1600 mV
110010 1632 mV
110011 1664 mV
110100 1696 mV
110101 1728 mV
110110 1760 mV
110111 1792 mV
111000 1824 mV
111001 1856 mV
111010 1888 mV
111011 1920 mV
111100 1952 mV
111101 1984 mV
111110 2016 mV
111111 Ext. VREF AIO
Table 7-24 VREF Range
VCC VREF Range
1.71 V - 2.3 V 32 mV - 1.504 V

2.3 V - 5.5 V

32 mV - 2.016 V