SCPS286 July   2025 TPLD2001

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Bus Timing Requirements
    9. 5.9 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.3.1 3-Bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-Bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-Bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.5.1 4-Bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing blocks
        1. 7.3.4.1 3-Bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Comparator Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Analog Comparators
        1. 7.3.11.1 Discrete Analog Comparator (ACMP)
        2. 7.3.11.2 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Analog Multiplexer (AMUX)
      15. 7.3.15 Oscillators
        1. 7.3.15.1 2kHz Fixed Frequency Oscillator
        2. 7.3.15.2 2MHz Fixed Frequency Oscillator
        3. 7.3.15.3 25MHz Fixed Frequency Oscillator
        4. 7.3.15.4 Oscillator Power Modes
      16. 7.3.16 Serial Communications
        1. 7.3.16.1 I2C Mode
        2. 7.3.16.2 SPI Mode
        3. 7.3.16.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP)
        3. 7.4.4.3 Intel HEX File Format
        4. 7.4.4.4 TPLD2001 Registers
          1. 7.4.4.4.1 TPLD2001_User Registers
          2. 7.4.4.4.2 TPLD2001_Cfg_0 Registers
          3. 7.4.4.4.3 TPLD2001_Cfg_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data
7.4.4.4.1 TPLD2001_User Registers

Table 7-38 lists the memory-mapped registers for the TPLD2001_User registers. All register offset addresses not listed in Table 7-38 should be considered as reserved locations and the register contents should not be modified.

Table 7-38 TPLD2001_USER Registers
OffsetAcronymBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0hDEVICE_ID0DEVICE_ID_MSB
1hDEVICE_ID1DEVICE_ID_LSB
2hDEVICE_ID2DEVICE_ID_RSVD
3hDEVICE_ID3DEVICE_ID_REV
4hDEVICE_ID4DEVICE_ID4
5hDEVICE_ID5DEVICE_ID5
6hDEVICE_ID6DEVICE_ID6
7hDEVICE_ID7DEVICE_ID7
10hCNT0_COUNTCNT0_COUNT
11hCNT1_COUNTCNT1_COUNT
12hCNT2_COUNTCNT2_COUNT
13hCNT3_COUNTCNT3_COUNT
14hCNT4_COUNT_LSBCNT4_COUNT_LSB
15hCNT4_COUNT_MSBCNT4_COUNT_MSB
16hCNT5_COUNT_LSBCNT5_COUNT_LSB
17hCNT5_COUNT_MSBCNT5_COUNT_MSB
18hCNT6_COUNTCNT6_COUNT
19hCNT7_COUNTCNT7_COUNT
1AhCNT8_COUNTCNT8_COUNT
1BhCNT9_COUNTCNT9_COUNT
20hCNT0_DATACNT0_DATA
21hCNT1_DATACNT1_DATA
22hCNT2_DATACNT2_DATA
23hCNT3_DATACNT3_DATA
24hCNT4_DATA_LSBCNT4_DATA_LSB
25hCNT4_DATA_MSBCNT4_DATA_MSB
26hCNT5_DATA_LSBCNT5_DATA_LSB
27hCNT5_DATA_MSBCNT5_DATA_MSB
28hCNT6_DATACNT6_DATA
29hCNT7_DATACNT7_DATA
2AhCNT8_DATACNT8_DATA
2BhCNT9_DATACNT9_DATA
30hWDT_TIMEOUT_DATAWATCHDOG_TIMEOUT_DATA
31hWDT_OUTPUT_DATAWATCHDOG_OUTPUT_DATA
32hWDT_STATUSRESERVEDWDT_STATUS
40hPGEN_DATA_LSBPGEN_DATA_LSB
41hPGEN_DATA_MSBPGEN_DATA_MSB
50hSTATE_MACHINERESERVEDCURRENT_STATE
51hSTATE0_OUTSTATE0_OUT
52hSTATE1_OUTSTATE1_OUT
53hSTATE2_OUTSTATE2_OUT
54hSTATE3_OUTSTATE3_OUT
55hSTATE4_OUTSTATE4_OUT
56hSTATE5_OUTSTATE5_OUT
57hSTATE6_OUTSTATE6_OUT
58hSTATE7_OUTSTATE7_OUT
70hVREF_ACMP0RESERVEDVREF_ACMP0
71hVREF_ACMP1RESERVEDVREF_ACMP1
72hVREF_ACMP2RESERVEDVREF_ACMP2
73hVREF_ACMP3RESERVEDVREF_ACMP3
74hVREF_McACMP0_0RESERVEDVREF_McACMP0_0
75hVREF_McACMP0_1RESERVEDVREF_McACMP0_1
76hVREF_McACMP1_0RESERVEDVREF_McACMP1_0
77hVREF_McACMP1_1RESERVEDVREF_McACMP1_1
78hVREF_McACMP2_0RESERVEDVREF_McACMP2_0
79hVREF_McACMP2_1RESERVEDVREF_McACMP2_1
7AhVREF_McACMP3_0RESERVEDVREF_McACMP3_0
7BhVREF_McACMP3_1RESERVEDVREF_McACMP3_1
E0hVIRTUAL_INPUTVIRTUAL_IN
E1hVIRTUAL_OUTPUTVIRTUAL_OUT
FDhSER_COMM_CFGRESERVEDADDR_INC
FEhCRC_STATUSERR_CNTRESERVEDERR_FLAG
FFhSER_COMM_WR_MASKSER_COMM_WR_MASK

Complex bit access types are encoded to fit into small table cells. Table 7-39 shows the codes that are used for access types in this section.

Table 7-39 TPLD2001_User Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

4.4.1.1 DEVICE_ID0 Register (Offset = 0h) [Reset = 20h]

DEVICE_ID0 is shown in Table 7-40.

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Table 7-40 DEVICE_ID0 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID_MSBR20h

4.4.1.2 DEVICE_ID1 Register (Offset = 1h) [Reset = 01h]

DEVICE_ID1 is shown in Table 7-41.

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Table 7-41 DEVICE_ID1 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID_LSBR1h

4.4.1.3 DEVICE_ID2 Register (Offset = 2h) [Reset = 00h]

DEVICE_ID2 is shown in Table 7-42.

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Table 7-42 DEVICE_ID2 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID_RSVDR0h

4.4.1.4 DEVICE_ID3 Register (Offset = 3h) [Reset = 00h]

DEVICE_ID3 is shown in Table 7-43.

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Table 7-43 DEVICE_ID3 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID_REVR0h

4.4.1.5 DEVICE_ID4 Register (Offset = 4h) [Reset = X0h]

DEVICE_ID4 is shown in Table 7-44.

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Table 7-44 DEVICE_ID4 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID4RXh

4.4.1.6 DEVICE_ID5 Register (Offset = 5h) [Reset = X0h]

DEVICE_ID5 is shown in Table 7-45.

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Table 7-45 DEVICE_ID5 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID5RXh

4.4.1.7 DEVICE_ID6 Register (Offset = 6h) [Reset = X0h]

DEVICE_ID6 is shown in Table 7-46.

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Table 7-46 DEVICE_ID6 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID6RXh

4.4.1.8 DEVICE_ID7 Register (Offset = 7h) [Reset = X0h]

DEVICE_ID7 is shown in Table 7-47.

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Table 7-47 DEVICE_ID7 Register Field Descriptions
BitFieldTypeResetDescription
7:0DEVICE_ID7RXh

4.4.1.9 CNT0_COUNT Register (Offset = 10h) [Reset = X0h]

CNT0_COUNT is shown in Table 7-48.

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Table 7-48 CNT0_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT0_COUNTRXh

4.4.1.10 CNT1_COUNT Register (Offset = 11h) [Reset = X0h]

CNT1_COUNT is shown in Table 7-49.

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Table 7-49 CNT1_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT1_COUNTRXh

4.4.1.11 CNT2_COUNT Register (Offset = 12h) [Reset = X0h]

CNT2_COUNT is shown in Table 7-50.

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Table 7-50 CNT2_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT2_COUNTRXh

4.4.1.12 CNT3_COUNT Register (Offset = 13h) [Reset = X0h]

CNT3_COUNT is shown in Table 7-51.

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Table 7-51 CNT3_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT3_COUNTRXh

4.4.1.13 CNT4_COUNT_LSB Register (Offset = 14h) [Reset = X0h]

CNT4_COUNT_LSB is shown in Table 7-52.

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Table 7-52 CNT4_COUNT_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT4_COUNT_LSBRXh

4.4.1.14 CNT4_COUNT_MSB Register (Offset = 15h) [Reset = X0h]

CNT4_COUNT_MSB is shown in Table 7-53.

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Table 7-53 CNT4_COUNT_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT4_COUNT_MSBRXh

4.4.1.15 CNT5_COUNT_LSB Register (Offset = 16h) [Reset = X0h]

CNT5_COUNT_LSB is shown in Table 7-54.

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Table 7-54 CNT5_COUNT_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT5_COUNT_LSBRXh

4.4.1.16 CNT5_COUNT_MSB Register (Offset = 17h) [Reset = X0h]

CNT5_COUNT_MSB is shown in Table 7-55.

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Table 7-55 CNT5_COUNT_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT5_COUNT_MSBRXh

4.4.1.17 CNT6_COUNT Register (Offset = 18h) [Reset = X0h]

CNT6_COUNT is shown in Table 7-56.

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Table 7-56 CNT6_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT6_COUNTRXh

4.4.1.18 CNT7_COUNT Register (Offset = 19h) [Reset = X0h]

CNT7_COUNT is shown in Table 7-57.

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Table 7-57 CNT7_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT7_COUNTRXh

4.4.1.19 CNT8_COUNT Register (Offset = 1Ah) [Reset = X0h]

CNT8_COUNT is shown in Table 7-58.

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Table 7-58 CNT8_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT8_COUNTRXh

4.4.1.20 CNT9_COUNT Register (Offset = 1Bh) [Reset = X0h]

CNT9_COUNT is shown in Table 7-59.

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Table 7-59 CNT9_COUNT Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT9_COUNTRXh

4.4.1.21 CNT0_DATA Register (Offset = 20h) [Reset = X0h]

CNT0_DATA is shown in Table 7-60.

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Table 7-60 CNT0_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT0_DATAR/WXh

4.4.1.22 CNT1_DATA Register (Offset = 21h) [Reset = X0h]

CNT1_DATA is shown in Table 7-61.

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Table 7-61 CNT1_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT1_DATAR/WXh

4.4.1.23 CNT2_DATA Register (Offset = 22h) [Reset = X0h]

CNT2_DATA is shown in Table 7-62.

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Table 7-62 CNT2_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT2_DATAR/WXh

4.4.1.24 CNT3_DATA Register (Offset = 23h) [Reset = X0h]

CNT3_DATA is shown in Table 7-63.

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Table 7-63 CNT3_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT3_DATAR/WXh

4.4.1.25 CNT4_DATA_LSB Register (Offset = 24h) [Reset = X0h]

CNT4_DATA_LSB is shown in Table 7-64.

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Table 7-64 CNT4_DATA_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT4_DATA_LSBR/WXh

4.4.1.26 CNT4_DATA_MSB Register (Offset = 25h) [Reset = X0h]

CNT4_DATA_MSB is shown in Table 7-65.

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Table 7-65 CNT4_DATA_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT4_DATA_MSBR/WXh

4.4.1.27 CNT5_DATA_LSB Register (Offset = 26h) [Reset = X0h]

CNT5_DATA_LSB is shown in Table 7-66.

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Table 7-66 CNT5_DATA_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT5_DATA_LSBR/WXh

4.4.1.28 CNT5_DATA_MSB Register (Offset = 27h) [Reset = X0h]

CNT5_DATA_MSB is shown in Table 7-67.

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Table 7-67 CNT5_DATA_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT5_DATA_MSBR/WXh

4.4.1.29 CNT6_DATA Register (Offset = 28h) [Reset = X0h]

CNT6_DATA is shown in Table 7-68.

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Table 7-68 CNT6_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT6_DATAR/WXh

4.4.1.30 CNT7_DATA Register (Offset = 29h) [Reset = X0h]

CNT7_DATA is shown in Table 7-69.

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Table 7-69 CNT7_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT7_DATAR/WXh

4.4.1.31 CNT8_DATA Register (Offset = 2Ah) [Reset = X0h]

CNT8_DATA is shown in Table 7-70.

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Table 7-70 CNT8_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT8_DATAR/WXh

4.4.1.32 CNT9_DATA Register (Offset = 2Bh) [Reset = X0h]

CNT9_DATA is shown in Table 7-71.

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Table 7-71 CNT9_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0CNT9_DATAR/WXh

4.4.1.33 WDT_TIMEOUT_DATA Register (Offset = 30h) [Reset = X0h]

WDT_TIMEOUT_DATA is shown in Table 7-72.

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Table 7-72 WDT_TIMEOUT_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0WATCHDOG_TIMEOUT_DATAR/WXh

4.4.1.34 WDT_OUTPUT_DATA Register (Offset = 31h) [Reset = X0h]

WDT_OUTPUT_DATA is shown in Table 7-73.

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Table 7-73 WDT_OUTPUT_DATA Register Field Descriptions
BitFieldTypeResetDescription
7:0WATCHDOG_OUTPUT_DATAR/WXh

4.4.1.35 WDT_STATUS Register (Offset = 32h) [Reset = X0h]

WDT_STATUS is shown in Table 7-74.

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Table 7-74 WDT_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0h Reserved
0WDT_STATUSR/WXh Watchdog fault/timeout output

4.4.1.36 PGEN_DATA_LSB Register (Offset = 40h) [Reset = X0h]

PGEN_DATA_LSB is shown in Table 7-75.

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Table 7-75 PGEN_DATA_LSB Register Field Descriptions
BitFieldTypeResetDescription
7:0PGEN_DATA_LSBR/WXh

4.4.1.37 PGEN_DATA_MSB Register (Offset = 41h) [Reset = X0h]

PGEN_DATA_MSB is shown in Table 7-76.

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Table 7-76 PGEN_DATA_MSB Register Field Descriptions
BitFieldTypeResetDescription
7:0PGEN_DATA_MSBR/WXh

4.4.1.38 STATE_MACHINE Register (Offset = 50h) [Reset = X0h]

STATE_MACHINE is shown in Table 7-77.

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Table 7-77 STATE_MACHINE Register Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR0h Reserved
2:0CURRENT_STATER/WXh

4.4.1.39 STATE0_OUT Register (Offset = 51h) [Reset = X0h]

STATE0_OUT is shown in Table 7-78.

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Table 7-78 STATE0_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE0_OUTR/WXh

4.4.1.40 STATE1_OUT Register (Offset = 52h) [Reset = X0h]

STATE1_OUT is shown in Table 7-79.

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Table 7-79 STATE1_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE1_OUTR/WXh

4.4.1.41 STATE2_OUT Register (Offset = 53h) [Reset = X0h]

STATE2_OUT is shown in Table 7-80.

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Table 7-80 STATE2_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE2_OUTR/WXh

4.4.1.42 STATE3_OUT Register (Offset = 54h) [Reset = X0h]

STATE3_OUT is shown in Table 7-81.

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Table 7-81 STATE3_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE3_OUTR/WXh

4.4.1.43 STATE4_OUT Register (Offset = 55h) [Reset = X0h]

STATE4_OUT is shown in Table 7-82.

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Table 7-82 STATE4_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE4_OUTR/WXh

4.4.1.44 STATE5_OUT Register (Offset = 56h) [Reset = X0h]

STATE5_OUT is shown in Table 7-83.

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Table 7-83 STATE5_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE5_OUTR/WXh

4.4.1.45 STATE6_OUT Register (Offset = 57h) [Reset = X0h]

STATE6_OUT is shown in Table 7-84.

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Table 7-84 STATE6_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE6_OUTR/WXh

4.4.1.46 STATE7_OUT Register (Offset = 58h) [Reset = X0h]

STATE7_OUT is shown in Table 7-85.

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Table 7-85 STATE7_OUT Register Field Descriptions
BitFieldTypeResetDescription
7:0STATE7_OUTR/WXh

4.4.1.47 VREF_ACMP0 Register (Offset = 70h) [Reset = X0h]

VREF_ACMP0 is shown in Table 7-86.

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Table 7-86 VREF_ACMP0 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_ACMP0R/WXh

4.4.1.48 VREF_ACMP1 Register (Offset = 71h) [Reset = X0h]

VREF_ACMP1 is shown in Table 7-87.

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Table 7-87 VREF_ACMP1 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_ACMP1R/WXh

4.4.1.49 VREF_ACMP2 Register (Offset = 72h) [Reset = X0h]

VREF_ACMP2 is shown in Table 7-88.

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Table 7-88 VREF_ACMP2 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_ACMP2R/WXh

4.4.1.50 VREF_ACMP3 Register (Offset = 73h) [Reset = X0h]

VREF_ACMP3 is shown in Table 7-89.

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Table 7-89 VREF_ACMP3 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_ACMP3R/WXh

4.4.1.51 VREF_McACMP0_0 Register (Offset = 74h) [Reset = X0h]

VREF_McACMP0_0 is shown in Table 7-90.

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Table 7-90 VREF_McACMP0_0 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP0_0R/WXh

4.4.1.52 VREF_McACMP0_1 Register (Offset = 75h) [Reset = X0h]

VREF_McACMP0_1 is shown in Table 7-91.

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Table 7-91 VREF_McACMP0_1 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP0_1R/WXh

4.4.1.53 VREF_McACMP1_0 Register (Offset = 76h) [Reset = X0h]

VREF_McACMP1_0 is shown in Table 7-92.

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Table 7-92 VREF_McACMP1_0 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP1_0R/WXh

4.4.1.54 VREF_McACMP1_1 Register (Offset = 77h) [Reset = X0h]

VREF_McACMP1_1 is shown in Table 7-93.

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Table 7-93 VREF_McACMP1_1 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP1_1R/WXh

4.4.1.55 VREF_McACMP2_0 Register (Offset = 78h) [Reset = X0h]

VREF_McACMP2_0 is shown in Table 7-94.

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Table 7-94 VREF_McACMP2_0 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP2_0R/WXh

4.4.1.56 VREF_McACMP2_1 Register (Offset = 79h) [Reset = X0h]

VREF_McACMP2_1 is shown in Table 7-95.

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Table 7-95 VREF_McACMP2_1 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP2_1R/WXh

4.4.1.57 VREF_McACMP3_0 Register (Offset = 7Ah) [Reset = X0h]

VREF_McACMP3_0 is shown in Table 7-96.

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Table 7-96 VREF_McACMP3_0 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP3_0R/WXh

4.4.1.58 VREF_McACMP3_1 Register (Offset = 7Bh) [Reset = X0h]

VREF_McACMP3_1 is shown in Table 7-97.

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Table 7-97 VREF_McACMP3_1 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0h Reserved
5:0VREF_McACMP3_1R/WXh

4.4.1.59 VIRTUAL_INPUT Register (Offset = E0h) [Reset = X0h]

VIRTUAL_INPUT is shown in Table 7-98.

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Table 7-98 VIRTUAL_INPUT Register Field Descriptions
BitFieldTypeResetDescription
7:0VIRTUAL_INR/WXh

4.4.1.60 VIRTUAL_OUTPUT Register (Offset = E1h) [Reset = X0h]

VIRTUAL_OUTPUT is shown in Table 7-99.

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Table 7-99 VIRTUAL_OUTPUT Register Field Descriptions
BitFieldTypeResetDescription
7:0VIRTUAL_OUTR/WXh

4.4.1.61 SER_COMM_CFG Register (Offset = FDh) [Reset = X0h]

SER_COMM_CFG is shown in Table 7-100.

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Table 7-100 SER_COMM_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0h Reserved
0ADDR_INCR/WXh Address auto-incrementing disable
  • 0h = Enabled
  • 1h = Disabled

4.4.1.62 CRC_STATUS Register (Offset = FEh) [Reset = X0h]

CRC_STATUS is shown in Table 7-101.

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Table 7-101 CRC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
7:5ERR_CNTR/W0h
4:1RESERVEDR0h Reserved
0ERR_FLAGR/WXh

4.4.1.63 SER_COMM_WR_MASK Register (Offset = FFh) [Reset = X0h]

SER_COMM_WR_MASK is shown in Table 7-102.

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Table 7-102 SER_COMM_WR_MASK Register Field Descriptions
BitFieldTypeResetDescription
7:0SER_COMM_WR_MASKR/WXh