SCPS286 July   2025 TPLD2001

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Bus Timing Requirements
    9. 5.9 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.3.1 3-Bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-Bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-Bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.5.1 4-Bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing blocks
        1. 7.3.4.1 3-Bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Comparator Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Analog Comparators
        1. 7.3.11.1 Discrete Analog Comparator (ACMP)
        2. 7.3.11.2 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Analog Multiplexer (AMUX)
      15. 7.3.15 Oscillators
        1. 7.3.15.1 2kHz Fixed Frequency Oscillator
        2. 7.3.15.2 2MHz Fixed Frequency Oscillator
        3. 7.3.15.3 25MHz Fixed Frequency Oscillator
        4. 7.3.15.4 Oscillator Power Modes
      16. 7.3.16 Serial Communications
        1. 7.3.16.1 I2C Mode
        2. 7.3.16.2 SPI Mode
        3. 7.3.16.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP)
        3. 7.4.4.3 Intel HEX File Format
        4. 7.4.4.4 TPLD2001 Registers
          1. 7.4.4.4.1 TPLD2001_User Registers
          2. 7.4.4.4.2 TPLD2001_Cfg_0 Registers
          3. 7.4.4.4.3 TPLD2001_Cfg_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

5.6 Supply Current Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC = 1.8V ± 0.09V VCC = 3.3V ± 0.3V VCC = 5V ± 0.5V UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Standby
ICC Standby Inputs = static,
Outputs = open,
IO = 0,
OSC powered off,
ACMP powered off		 2.41 3.26 4.22 µA
ICC Standby, Bandgap enabled Bandgap force on
 4.53 5.38 6.35 µA
Oscillator
ICC OSC0 enabled: 2kHz Predivide = 1 0.63 0.70 1.11 µA
Predivide = 2 0.62 0.72 1.12
Predivide = 4 0.62 0.72 1.09
Predivide = 8 0.64 0.72 1.06
ICC OSC1 enabled: 2MHz Predivide = 1 31.6 34.2 40.7 µA
Predivide = 2 28.5 31.1 37.7
Predivide = 4 26.4 29.1 35.8
Predivide = 8 25.4 28.1 34.9
ICC OSC2 enabled: 25MHz Predivide = 1 508 508 508 µA
Predivide = 2 349 349 349
Predivide = 4 268 268 268
Predivide = 8 228 228 228
ICC OSC2 enabled: 25MHz Normal startup,
OSC output idle		 15.5 15.7 16.0 µA
ICC OSC2 enabled: 25MHz Fast startup enabled,
OSC output idle		 23.5 23.7 24.0 µA
Analog Comparator - Discrete Analog Comparator
ICC Discrete analog comparator (ACMP) External VREF (32mV),
IN+ = 0V,
Low bandwidth mode disabled		 3.46 3.56 3.63 µA
External VREF (32mV),
IN+ = VCC,
Low bandwidth mode disabled		 4.09 4.17 4.31
External VREF (32mV),
IN+ = 0V,
Low bandwidth mode enabled		 0.82 0.83 0.83
External VREF (32mV),
IN+ = VCC,
Low bandwidth mode enabled		 0.81 0.81 0.83
Analog Comparator - Multi-channel Analog Comparator
ICC Multi-channel sampling analog comparator (McACMP) 1 channel,
External VREF (32mV),
IN+ = 0V,
Low bandwidth mode disabled		 3.32 3.44 3.53 µA
1 channel,
External VREF (32mV),
IN+ = VCC,
Low bandwidth mode disabled		 3.93 4.06 4.19
1 channel,
External VREF (32mV),
IN+ = 0V,
Low bandwidth mode enabled		 0.78 0.81 0.83
1 channel,
External VREF (32mV),
IN+ = VCC,
Low bandwidth mode enabled		 0.79 0.82 0.85
4 channel continuous sampling,
External VREF (32mV),
IN+ = 0V,
OSC = 2kHz		 1.36 1.47 1.83
4 channel continuous sampling,
External VREF (32mV),
IN+ = 0V,
OSC = 100kHz		 35.4 38.0 44.7
Voltage Reference
ICC Voltage reference (VREF) Internal VREF (32mV to 2016mV) 6.92 7.04 7.14 µA
Analog Temperature Sensor
ICC Analog temperature sensor (TS) Temperature sensor enabled 3.93 4.05 4.14 µA
Analog Multiplexer
ICC Analog multiplexer (AMUX) Analog mux enabled µA