SCPS286 July   2025 TPLD2001

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Bus Timing Requirements
    9. 5.9 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.3.1 3-Bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-Bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-Bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.5.1 4-Bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing blocks
        1. 7.3.4.1 3-Bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Comparator Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Analog Comparators
        1. 7.3.11.1 Discrete Analog Comparator (ACMP)
        2. 7.3.11.2 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Analog Multiplexer (AMUX)
      15. 7.3.15 Oscillators
        1. 7.3.15.1 2kHz Fixed Frequency Oscillator
        2. 7.3.15.2 2MHz Fixed Frequency Oscillator
        3. 7.3.15.3 25MHz Fixed Frequency Oscillator
        4. 7.3.15.4 Oscillator Power Modes
      16. 7.3.16 Serial Communications
        1. 7.3.16.1 I2C Mode
        2. 7.3.16.2 SPI Mode
        3. 7.3.16.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP)
        3. 7.4.4.3 Intel HEX File Format
        4. 7.4.4.4 TPLD2001 Registers
          1. 7.4.4.4.1 TPLD2001_User Registers
          2. 7.4.4.4.2 TPLD2001_Cfg_0 Registers
          3. 7.4.4.4.3 TPLD2001_Cfg_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

5.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 TEST
CONDITIONS		 VCC MIN TYP MAX UNIT
Digital IO
tpd Delay Digital input Push-pull output Rising 1.8V ± 0.09V 32.4 ns
Falling 29.6
Rising 3.3V ± 0.3V 19.2
Falling 17.0
Rising 5V ± 0.5V 15.2
Falling 14.4
tpd Delay Digital input with Schmitt trigger Push-pull output Rising 1.8V ± 0.09V 38.2 ns
Falling 36.5
Rising 3.3V ± 0.3V 23.4
Falling 22.5
Rising 5V ± 0.5V 19.2
Falling 19.8
tpd Delay Low-voltage digital input Push-pull output Rising 1.8V ± 0.09V 32.3 ns
Falling 32.7
Rising 3.3V ± 0.3V 21.3
Falling 21.8
Rising 5V ± 0.5V 18.5
Falling 18.1
tpd Delay Digital input Open-drain NMOS output Rising 1.8V ± 0.09V ns
Falling 26.3
Rising 3.3V ± 0.3V
Falling 17.6
Rising 5V ± 0.5V
Falling 15.4
tpd Delay Output enable from pin OE Push-pull output Hi-Z to 1
1.8V ± 0.09V

 ns

3.3V ± 0.3V

5V ± 0.5V
Hi-Z to 0
1.8V ± 0.09V

 ns

3.3V ± 0.3V

5V ± 0.5V
Configurable Use Logic
tpd Delay 2-bit LUT IN OUT Rising 1.8V ± 0.09V 1.0 ns
Falling 0.9
Rising 3.3V ± 0.3V 1.0
Falling 0.9
Rising 5V ± 0.5V 1.0
Falling 0.9
tpd Delay 3-bit LUT IN OUT Rising 1.8V ± 0.09V 0.9 ns
Falling 0.7
Rising 3.3V ± 0.3V 0.9
Falling 0.7
Rising 5V ± 0.5V 0.9
Falling 0.7
tpd Delay 4-bit LUT IN OUT Rising 1.8V ± 0.09V 1.1 ns
Falling 1.0
Rising 3.3V ± 0.3V 1.1
Falling 1.0
Rising 5V ± 0.5V 1.1
Falling 1.0
tpd Delay DFF/Latch CLK Q Rising 1.8V ± 0.09V 1.5 ns
Falling 1.6
Rising 3.3V ± 0.3V 1.5
Falling 1.6
Rising 5V ± 0.5V 1.6
Falling 1.7
tpd Delay DFF/Latch nRST/nSET Q Rising 1.8V ± 0.09V 4.6 ns
Falling 4.6
Rising 3.3V ± 0.3V 4.7
Falling 4.6
Rising 5V ± 0.5V 4.7
Falling 4.6
tpd Delay Pattern generator CLK OUT Rising 1.8V ± 0.09V 1.7 ns
Falling 1.7
Rising 3.3V ± 0.3V 1.5
Falling 1.6
Rising 5V ± 0.5V 1.7
Falling 1.7
Counter/Delay
tpd Delay Shift register CLK OUT Rising 1.8V ± 0.09V 1.5 ns
Falling 1.6
Rising 3.3V ± 0.3V 1.5
Falling 1.6
Rising 5V ± 0.5V 1.5
Falling 1.6
tpd Delay Shift register nRST OUT Rising 1.8V ± 0.09V ns
Falling 2.2
Rising 3.3V ± 0.3V
Falling 2.2
Rising 5V ± 0.5V
Falling 2.2
tpd Delay Counter - Delay mode Rising edge of IN Rising edge of OUT Falling edge triggered 1.8V ± 0.09V 3.7 ns
Falling edge of IN Falling edge of OUT Rising edge triggered 2.9
Rising edge of IN Rising edge of OUT Falling edge triggered 3.3V ± 0.3V 3.7
Falling edge of IN Falling edge of OUT Rising edge triggered 2.9
Rising edge of IN Rising edge of OUT Falling edge triggered 5V ± 0.5V 3.7
Falling edge of IN Falling edge of OUT Rising edge triggered 2.9
tpw Pulse width Counter - Edge detect mode Rising edge of OUT Falling edge of OUT Rising edge detect
1.8V ± 0.09V

 19.7 ns

3.3V ± 0.3V

 19.8

5V ± 0.5V

 19.8
Falling edge detect
1.8V ± 0.09V

 19.9

3.3V ± 0.3V

 19.9

5V ± 0.5V

 19.9
Both edge detect
1.8V ± 0.09V

 19.9

3.3V ± 0.3V

 20.0

5V ± 0.5V

 20.0
State Machine
tst_pw State transition pulse width
1.8V ± 0.09V

 22.0 ns

3.3V ± 0.3V

 22.0

5V ± 0.5V

 22.0
tst_dly State transition delay
1.8V ± 0.09V

 61.5 ns

3.3V ± 0.3V

 51.3

5V ± 0.5V

 48.6
Oscillator
ferr Oscillator frequency error OSC0 2kHz
1.8V ± 0.09V

 -5 5 %

3.3V ± 0.3V

 -5 5

5V ± 0.5V

 -5 5
OSC1 2MHz
1.8V ± 0.09V

 -5 5 %

3.3V ± 0.3V

 -5 5

5V ± 0.5V

 -5 5
OSC2 25MHz
1.8V ± 0.09V

 -5 5 %

3.3V ± 0.3V

 -5 5

5V ± 0.5V

 -5 5
td_osc Oscillator startup delay OSC0 2kHz
1.8V ± 0.09V

 364.2 µs

3.3V ± 0.3V

 315.8

5V ± 0.5V

 319.9
td_osc Oscillator startup delay OSC1 2MHz,
Bandgap force on
1.8V ± 0.09V

 0.52 µs

3.3V ± 0.3V

 0.49

5V ± 0.5V

 0.53
td_osc Oscillator startup delay OSC2 25MHz,
Bandgap force on
1.8V ± 0.09V

 2.80 µs

3.3V ± 0.3V

 2.69

5V ± 0.5V

 2.58
td_osc Oscillator startup delay OSC2 25MHz, 
Fast startup enabled
1.8V ± 0.09V

 0.38 µs

3.3V ± 0.3V

 0.37

5V ± 0.5V

 0.34
td_bg Bandgap startup delay Bandgap auto on
1.8V ± 0.09V

 42.0 µs

3.3V ± 0.3V

 42.0

5V ± 0.5V

 42.0
tset_osc Oscillator startup settling time OSC0 2kHz
1.8V ± 0.09V

 164.0 µs

3.3V ± 0.3V

 165.2

5V ± 0.5V

 166.1
OSC1 2MHz
1.8V ± 0.09V

 0.8 µs

3.3V ± 0.3V

 0.7

5V ± 0.5V

 0.7
OSC2 25MHz
1.8V ± 0.09V

 0.1 µs

3.3V ± 0.3V

 0.1

5V ± 0.5V

 0.1
td_err Delay error OSC (Forced power on) 1.71V to 5.5V 0 1 CLK cycle
Programmable Filter
tpflt_pw Pulse width Programmable filter - Edge detect mode Rising edge of OUT Falling edge of OUT 1 cell
1.8V ± 0.09V

 138.2 ns

3.3V ± 0.3V

 138.1

5V ± 0.5V

 138.3
2 cells
1.8V ± 0.09V

 238.4 ns

3.3V ± 0.3V

 238.2

5V ± 0.5V

 238.0
3 cells
1.8V ± 0.09V

 336.9 ns

3.3V ± 0.3V

 336.4

5V ± 0.5V

 336.6
4 cells
1.8V ± 0.09V

 434.3 ns

3.3V ± 0.3V

 434.2

5V ± 0.5V

 434.5
tpflt_pd Delay Programmable filter - Edge detect mode Any cells
1.8V ± 0.09V

 63.4 ns

3.3V ± 0.3V

 63.4

5V ± 0.5V

 63.4
tpflt_d Delay Programmable filter - Both edge delay mode Rising/Falling edge of IN Rising/Falling edge of OUT 1 cell
1.8V ± 0.09V

 153.4 ns

3.3V ± 0.3V

 153.5

5V ± 0.5V

 153.6
2 cells
1.8V ± 0.09V

 253.7 ns

3.3V ± 0.3V

 253.9

5V ± 0.5V

 253.6
3 cells
1.8V ± 0.09V

 352.4 ns

3.3V ± 0.3V

 352.2

5V ± 0.5V

 352.7
4 cells
1.8V ± 0.09V

 450.2 ns

3.3V ± 0.3V

 449.9

5V ± 0.5V

 450.3
Analog Multiplexer
Frequency response (switch on) Y or A, B A, B or Y RL = 50Ω,
fin = sine wave		 1.8V ± 0.09V MHz
2.5V ± 0.2V
3.3V ± 0.3V
5V ± 0.5V
Crosstalk (between switches) A or B B or A RL = 50Ω,
fin = 10MHz (sine wave)		 1.8V ± 0.09V dB
2.5V ± 0.2V
3.3V ± 0.3V
5V ± 0.5V
Feedthrough attentuation (switch off) Y or A, B A, B or Y CL = 5pF,
RL = 50Ω,
fin = 10MHz (sine wave)		 1.8V ± 0.09V dB
2.5V ± 0.2V
3.3V ± 0.3V
5V ± 0.5V
Charge injection IN Y CL = 0.1nF,
RL = 1MΩ		 3.3V 1.17 pC
5V 1.46
Total harmonic distortion Y or A, B A, B or Y VI = 0.5 × Vpp,
RL = 600Ω,
fin = 600Hz to 20kHz (sine wave)		 1.8V ± 0.09V 0.18 %
2.5V ± 0.2V 0.02
3.3V ± 0.3V 0.01
5V ± 0.5V 0.01
tpd(1) Delay Y or A, B A, B or Y 1.8V ± 0.09V 2.6 ns
2.5V ± 0.2V 1.6
3.3V ± 0.3V 1.2
5V ± 0.5V 1.0
ten(2) Enable time IN A or B 1.8V ± 0.09V 5.9 45.0 ns
2.5V ± 0.2V 3.8 36.2
3.3V ± 0.3V 3.4 33.8
5V ± 0.5V 2.6 30.8
tdis(3) Disable time 1.8V ± 0.09V 6.0 45.7
2.5V ± 0.2V 4.7 36.4
3.3V ± 0.3V 3.7 33.3
5V ± 0.5V 3.2 30.8
tB-M Break-before-make time IN Y IN = LOW to HIGH step
A, B = VCC/2,
RL = 50Ω,
CL = 35pF		 1.8V ± 0.09V 3.6 ns
2.5V ± 0.2V 2.6
3.3V ± 0.3V 2.0
5V ± 0.5V 1.5
(1) tpd is the slower of tPLH or tPHL. The delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). 
(2) ten is the slower of tPZL or tPZH.
(3) tdis is the slower of tPLZ or tPHZ.