SLASFM6 October   2026 TAS2573

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Software Power Modes Control and Software Reset
        3. 6.3.1.3 Efficiency and power saving modes
          1. 6.3.1.3.1 Noise Gate
          2. 6.3.1.3.2 Music Efficiency Mode
          3. 6.3.1.3.3 VDD Y-bridge
          4. 6.3.1.3.4 Class-H Boost
        4. 6.3.1.4 2S Battery Mode
        5. 6.3.1.5 Low voltage battery mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1 PurePath™ Console 3 Software
      2. 6.4.2 Playback Signal Path
        1. 6.4.2.1 Digital Signal Processor
          1. 6.4.2.1.1 Algorithm Blocks
          2. 6.4.2.1.2 Algorithm Features
          3. 6.4.2.1.3 Factory Calibration
        2. 6.4.2.2 Digital Volume Control and Amplifier Output Level
        3. 6.4.2.3 High Pass Filter
        4. 6.4.2.4 Class-D Amplifier
        5. 6.4.2.5 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.5.1 Voltage Limiter and Clipping protection
        6. 6.4.2.6 Tone Generator
      3. 6.4.3 Digital Audio Serial Interface
      4. 6.4.4 Boost
      5. 6.4.5 Speaker current and voltage (IV) sensing
      6. 6.4.6 Supply Voltage Monitors
      7. 6.4.7 Thermal Protection
      8. 6.4.8 Clocks and PLL
        1. 6.4.8.1 Auto clock based wakeup and clock errors
      9. 6.4.9 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 PAGE_0 Registers
    2. 7.2 PAGE_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
      4. 8.2.4 What to Do and What Not to Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Option Addendum
    2. 11.2 Tape and Reel Information

6.4.2.2 Digital Volume Control and Amplifier Output Level

The gain from audio input to speaker terminals is controlled by setting the amplifier’s analog gain level (AAMP), digital volume control (ADVC) and user volume control (AUSER). Equation 1 calculates the output voltage of the amplifier. Amplifier analog gain setting (AAMP) must be set before powering up the playback channel and must not be changed while the channel is active. The user volume control (AUSER) can be modified while the channel is active and is used for changing the output level dynamically based on user input. The digital volume control (ADVC) can be modified while the channel is active but only if the on chip DSP algorithms are disabled . When the on chip DSP algorithms are enabled, ADVC must be set before powering up the playback channel and must not be changed while the channel is active. Both the ADVC and AUSER allows for soft volume ramp up/down feature to allow for smooth transition of output voltage from one level to another.

Equation 1. VAMP=Input + AUSER + ADVC+AAMP dBV

where

  • VAMP is the amplifier output voltage in dBV
  • Input is the digital input amplitude in dB with respect to 0dBFS
  • AUSER is the user volume control setting, 18dB to -105dB in 0.5dB steps
  • ADVC is the digital volume control setting, 6dB to -110dB in 0.5dB steps
  • AAMP is the amplifier output level setting, -0.071dBV to 21.0dBV in 0.5017dBV steps.

Amplifier output level settings are presented in dBV (dB relative to 1Vrms) with a full scale digital audio input (0dBFS) and the digital volume control set to 0dB. Note that these levels are not achievable because of analog clipping in the amplifier, so the levels must be used to convey gain only.

Table 6-14 shows gain settings that can be programmed via the AMP_LVL register for AAMP. When AMP_LVL is set to less than 9dBV settings, the playback channel is automatically configured to low noise mode or receiver mode of operation.

Table 6-14 Amplifier Output Level Settings
AMP_LVL[5:0] FULL SCALE OUTPUT
dBV VPEAK (V)
0x00 21.000 15.9
0x01 20.498 15.0
0x02 19.997 14.1
0x03 19.495 13.3
0x04 18.993 12.6
... ... ...
0x27 1.434 1.7
0x28 0.932 1.6
0x29 0.430 1.5
0x2A -0.071 1.4
0x2B-0x3F Reserved Reserved

When a change in digital volume control (ADVC) occurs, the device ramps the volume to the new setting based on the DVC_SLEW_RATE register bits. If DVC_SLEW_RATE is set to 0x7FFFFF, volume ramp is disabled. This can be used to speed up start up, shutdown and digital volume changes when volume ramp is handled by the system host. When volume ramp is disabled, the input audio data stream must be held at digital silence during shutdown and power up of the device to avoid any clicks and pops.

The device can be put in software based mute by setting DVC_LEVEL to 0x000000 setting.

The digital voltage control registers DVC_LEVEL and DVC_SLEW_RATE registers can be configured using the PPC3 Software Section 6.4.1.

Table 6-15 Digital Volume Control
DVC_LEVEL[23:0] VOLUME (dB)
0x000000 Software MUTE
0x00000D (MIN) -110
... ...
0x400000 0 (default)
... ...
0x7FB261 (MAX) 6
Table 6-16 Digital Volume Ramp Rate
DVC_SLEW_RATE[23:0] RAMP RATE @ 48kHz (s)
0x00036A 1000ms
...
0x034A51 4ms (default)
...
0x7FFFFF 0 - Ramp disabled

The AUSER settings can be tuned using the PPC3 Software Section 6.4.1.