SLVSH22A May   2024  – September 2025 DRV8000-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUTx HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Short-circuit Protection
          3. 7.4.2.2.3 High-side Driver Overcurrent Protection
          4. 7.4.2.2.4 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.4.3 Half-bridge Register Control
        4. 7.4.4.4 Half-Bridge ITRIP Regulation
        5. 7.4.4.5 Half-bridge Protection and Diagnostics
          1. 7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.5.2 Half-bridge Open Load Detection
          3. 7.4.4.5.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short-circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IDRIVE Calculation Example
        2. 9.2.2.2 tDRIVE Calculation Example
        3. 9.2.2.3 Maximum PWM Switching Frequency
        4. 9.2.2.4 Current Shunt Amplifier Configuration
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Pre-Production Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

8.2 DRV8000-Q1_CNFG Registers

Table 8-14 lists the memory-mapped registers for the DRV8000-Q1_CNFG registers. All register offset addresses not listed in Table 8-14 should be considered as reserved locations and the register contents should not be modified.

Table 8-14 DRV8000-Q1_CNFG Registers
OffsetAcronymRegister NameSection
9hIC_CNFG1IC configuration register 1.Section 8.2.1
AhIC_CNFG2IC configuration register 2.Section 8.2.2
BhGD_CNFGGate driver configuration register.Section 8.2.3
ChGD_IDRV_CNFGIDRIVE setting configuration register.Section 8.2.4
DhGD_VGS_CNFGVGS detection configuration register.Section 8.2.5
EhGD_VDS_CNFGVDS monitoring configuration register.Section 8.2.6
FhGD_CSA_CNFGCSA configuration register.Section 8.2.7
10hGD_AGD_CNFGAdvanced smart gate driver configuration register.Section 8.2.8
11hGD_PDR_CNFGPropagation Delay Reduction configuration register.Section 8.2.9
12hGD_STC_CNFGSlew time control configuration register.Section 8.2.10
13hGD_SPARE_CNFG1Spare gate driver configuration register 1.Section 8.2.11
14hHB_ITRIP_DGHalf-bridge ITRIP deglitch configuration register 2.Section 8.2.12
15hHB_OUT_CNFG1Half-bridge output 5 and 6 configuration register.Section 8.2.13
16hHB_OUT_CNFG2Half-bridge output 1-4 configuration register.Section 8.2.14
17hHB_OCP_CNFGHalf-bridge overcurrent deglitch configuration register.Section 8.2.15
18hHB_OL_CNFG1Half-bridge active and passive open-load enable registerSection 8.2.16
19hHB_OL_CNFG2Half-bridge active open-load threshold select register.Section 8.2.17
1AhHB_SR_CNFGHalf-bridge slew rate configuration register.Section 8.2.18
1BhHB_ITRIP_CNFGHalf-bridge ITRIP configuration register 1.Section 8.2.19
1ChHB_ITRIP_FREQHalf-bridge ITRIP frequency configuration register 2.Section 8.2.20
1DhHS_HEAT_OUT_CNFGHigh-side and heater driver output configuration register.Section 8.2.21
1EhHS_OC_CNFGHigh-side driver overcurrent threshold configuration register.Section 8.2.22
1FhHS_OL_CNFGHigh-side driver open load threshold configuration register.Section 8.2.23
20hHS_REG_CNFG1High-side driver regulation configuration register.Section 8.2.24
21hHS_REG_CNFG2High-side driver regulation configuration register.Section 8.2.25
22hHS_PWM_FREQ_CNFGHigh-side driver PWM generator frequency configuration register.Section 8.2.26
23hHEAT_CNFGHeater configuration register.Section 8.2.27
24hEC_CNFGElectrochrome configuration register.Section 8.2.28
25hHS_REG_CNFG3High-side driver regulation configuration register.Section 8.2.29
26hSPARE_CNFG2Spare configurationSection 8.2.30
27hOUT1_HS_MODE_DCDuty cycle configuration for OUT1.Section 8.2.31
28hOUT2_HS_MODE_DCDuty cycle configuration for OUT2.Section 8.2.32

Complex bit access types are encoded to fit into small table cells. Table 8-15 shows the codes that are used for access types in this section.

Table 8-15 DRV8000-Q1_CNFG Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.2.1 IC_CNFG1 Register (Offset = 9h) [Reset = 0002h]

IC_CNFG1 is shown in Table 8-16.

Return to the Summary Table.

Includes configurations charge pump and watchdog, and fault levels and reactions for supply, charge pump, thermal, and watch dog faults.

Table 8-16 IC_CNFG1 Register Field Descriptions
BitFieldTypeResetDescription
15OTSD_MODER/W0h Sets overtemperature shutdown behavior. If any thermal cluster reaches OT, the device shuts down all drivers or affected drivers only (drivers in zone 3, for example).
0b = Global shutdown.
1b = Affected driver shutdown only.
14DIS_CPR/W0h When all output are off (OUTx_EN, EN_GD, HEAT_EN, EC_ON), the charge pump can be disabled, putting the device in a communication only mode.
0b = Charge pump enabled.
1b = Charge pump disabled.
13RSVDR0h Reserved.
12PVDD_OV_MODER/W0h PVDD supply overvoltage monitor mode.
0b = Latched fault.
1b = Automatic recovery.
11-10PVDD_OV_DGR/W0h PVDD supply overvoltage monitor deglitch time.
00b = 1 µs
01b = 2 µs
10b = 4 µs
11b = 8 µs
9PVDD_OV_LVLR/W0h PVDD supply overvoltage monitor threshold.
0b = 22 V
1b = 28 V
8VCP_UV_LVLR/W0h VCP charge pump undervoltage monitor threshold.
0b = 4.75 V
1b = 6.25 V
7-6CP_MODER/W0h Charge pump operating mode.
00b = Automatic switch between tripler and doubler mode.
01b = Always doubler mode.
10b = Always tripler mode.
11b = RSVD
5VCP_UV_MODER/W0h VCP charge pump undervoltage monitor mode.
0b = Latched fault.
1b = Automatic recovery.
4PVDD_UV_MODER/W0h PVDD supply undervoltage monitor mode.
0b = Latched fault.
1b = Automatic recovery.
3WD_ENR/W0h Watchdog timer enable.
0b = Watchdog timer disabled.
1b = Watchdog timer enabled.
2WD_FLT_MR/W0h Watchdog fault mode. Watchdog fault is cleared by CLR_FLT.
0b = Watchdog fault is reported to WD_FLT and WARN register bits. Drivers remain enabled and FAULT bit is not asserted.
1b = Watchdog fault is reported to WD_FLT and FAULT register bits. All drivers are disabled in response to watchdog fault.
1WD_WINR/W1h Watchdog timer window.
0b = 4 to 12 ms
1b = 10 to 100 ms
0EN_SSCR/W0h Spread spectrum clocking.
0b = Disabled.
1b = Enabled.

8.2.2 IC_CNFG2 Register (Offset = Ah) [Reset = 0000h]

IC_CNFG2 is shown in Table 8-17.

Return to the Summary Table.

Includes thermal cluster warning disable bits.

Table 8-17 IC_CNFG2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7ZONE4_OTW_H_DISR/W0h Disables the high overtemperature warning for zone 4.
Enabled = 0b
Disabled = 1b
6ZONE3_OTW_H_DISR/W0h Disables the high overtemperature warning for zone 3.
Enabled = 0b
Disabled = 1b
5ZONE2_OTW_H_DISR/W0h Disables the high overtemperature warning for zone 2.
Enabled = 0b
Disabled = 1b
4ZONE1_OTW_H_DISR/W0h Disables the high overtemperature warning for zone 1.
Enabled = 0b
Disabled = 1b
3ZONE4_OTW_L_DISR/W0h Disables the low overtemperature warning for zone 4.
Enabled = 0b
Disabled = 1b
2ZONE3_OTW_L_DISR/W0h Disables the low overtemperature warning for zone 3.
Enabled = 0b
Disabled = 1b
1ZONE2_OTW_L_DISR/W0h Disables the low overtemperature warning for zone 2.
Enabled = 0b
Disabled = 1b
0ZONE1_OTW_L_DISR/W0h Disables the low overtemperature warning for zone 1.
Enabled = 0b
Disabled = 1b

8.2.3 GD_CNFG Register (Offset = Bh) [Reset = 0000h]

GD_CNFG is shown in Table 8-18.

Return to the Summary Table.

General gate driver controls. Includes gate driver enable, bridge configuration, input pin modes, and open load enable.

Table 8-18 GD_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13IDRV_LO1R/W0h Enable low current IDRVN and IDRVP mode for half-bridge 1.
0b = IDRVP_1 and IDRVN_1 utilize standard values.
1b = IDRVP_1 and IDRVN_1 utilize low current values.
12IDRV_LO2R/W0h Enable low current IDRVN and IDRVP mode for half-bridge 2.
0b = IDRVP_2 and IDRVN_2 utilize standard values.
1b = IDRVP_2 and IDRVN_2 utilize low current values.
11PU_SH_1R/W0h Gate driver 1 pullup diagnostic current source.
Set EN_OLSC = 1b to use.
0b = Disabled.
1b = Enabled.
10PD_SH_1R/W0h Gate driver 1 pulldown diagnostic current source.
Set EN_OLSC = 1b to use.
0b = Disabled.
1b = Enabled.
9PU_SH_2R/W0h Gate driver 2 pullup diagnostic current source.
Set EN_OLSC = 1b to use.
0b = Disabled.
1b = Enabled.
8PD_SH_2R/W0h Gate driver 2 pulldown diagnostic current source.
Set EN_OLSC = 1b to use.
0b = Disabled.
1b = Enabled.
7RESERVEDR/W0h Reserved
6IN2_MODER/W0h Sets gate driver 2 control source.
0b = Input pin IN2.
1b = SPI control.
5IN1_MODER/W0h Sets gate driver 1 control source.
0b = Input pin IN1.
1b = SPI control.
4BRG_FWR/W0h Gate driver 1 and 2 control freewheeling setting. Settings shared between half-bridges 1 and 2.
0b = Low-side freewheeling
1b = High-side freewheeling.
3-2BRG_MODER/W0h Gate driver 1 and 2 input control mode.
00b = Independent half-bridge input control.
01b = PH/EN H-bridge input control.
10b = PWM H-bridge input control.
11b = Reserved.
1EN_OLSCR/W0h Offline open-load and short-circuit diagnostic enable.
0b = Disabled.
1b = VDS monitors set into real-time voltage monitor mode and diagnostics current sources enabled.
0EN_GDR/W0h Enable gate driver bit.
0b = Driver inputs are ignored and the gate driver passive pulldowns are enabled.
1b = Gate driver outputs are enabled and controlled by the digital inputs.

8.2.4 GD_IDRV_CNFG Register (Offset = Ch) [Reset = 4444h]

GD_IDRV_CNFG is shown in Table 8-19.

Return to the Summary Table.

Includes IDRIVE drive current levels for each half-bridge gate driver.

Table 8-19 GD_IDRV_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15-12IDRVP_1R/W4h Gate driver 1 peak source pullup current. Alternative low current value in parenthesis (IDRV_LO1).
0000b = 0.5 mA (50 µA)
0001b = 1 mA (110 µA)
0010b = 2 mA (170 µA)
0011b = 3 mA (230 µA)
0100b = 4 mA (290 µA)
0101b = 5 mA (350 µA)
0110b = 6 mA (410 µA)
0111b = 7 mA (600 µA)
1000b = 8 mA (725 µA)
1001b = 12 mA (850 µA)
1010b = 16 mA (1 mA)
1011b = 20 mA (1.2 mA)
1100b = 24 mA (1.4 mA)
1101b = 31 mA (1.6 mA)
1110b = 48 mA (1.8 mA)
1111b = 62 mA (2.3 mA)
11-8IDRVN_1R/W4h Gate driver 1 peak sink pulldown current. Alternative low current value in parenthesis (IDRV_LO1).
0000b = 0.5 mA (50 µA)
0001b = 1 mA (110 µA
0010b = 2 mA (170 µA
0011b = 3 mA (230 µA)
0100b = 4 mA (290 µA)
0101b = 5 mA (350 µA)
0110b = 6 mA (410 µA)
0111b = 7 mA (600 µA)
1000b = 8 mA (725 µA)
1001b = 12 mA (850 µA)
1010b = 16 mA (1 mA)
1011b = 20 mA (1.2 mA)
1100b = 24 mA (1.4 mA)
1101b = 31 mA (1.6 mA)
1110b = 48 mA (1.8 mA)
1111b = 62 mA (2.3 mA)
7-4IDRVP_2R/W4h Gate driver 2 peak source pullup current. Alternative low current value in parenthesis (IDRV_LO2).
0000b = 0.5 mA (50 µA)
0001b = 1 mA (110 µA)
0010b = 2 mA (170 µA)
0011b = 3 mA (230 µA)
0100b = 4 mA (290 µA)
0101b = 5 mA (350 µA)
0110b = 6 mA (410 µA)
0111b = 7 mA (600 µA)
1000b = 8 mA (725 µA)
1001b = 12 mA (850 µA)
1010b = 16 mA (1 mA)
1011b = 20 mA (1.2 mA)
1100b = 24 mA (1.4 mA)
1101b = 31 mA (1.6 mA)
1110b = 48 mA (1.8 mA)
1111b = 62 mA (2.3 mA)
3-0IDRVN_2R/W4h Gate driver 2 peak sink pulldown current. Alternative low current value in parenthesis (IDRV_LO2).
0000b = 0.5 mA (50 µA)
0001b = 1 mA (110 µA)
0010b = 2 mA (170 µA)
0011b = 3 mA (230 µA)
0100b = 4 mA (290 µA)
0101b = 5 mA (350 µA)
0110b = 6 mA (410 µA)
0111b = 7 mA (600 µA)
1000b = 8 mA (725 µA)
1001b = 12 mA (850 µA)
1010b = 16 mA (1 mA)
1011b = 20 mA (1.2 mA)
1100b = 24 mA (1.4 mA)
1101b = 31 mA (1.6 mA)
1110b = 48 mA (1.8 mA)
1111b = 62 mA (2.3 mA)

8.2.5 GD_VGS_CNFG Register (Offset = Dh) [Reset = 0030h]

GD_VGS_CNFG is shown in Table 8-20.

Return to the Summary Table.

VGS fault detection configurations.

Table 8-20 GD_VGS_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11VGS_INDR/W0h VGS independent shutdown mode enable.
Active for BRG_MODE = 00b.
0b = Disabled.
1b = Enabled. VGS gate fault only shuts down the associated half-bridge.
10-9VGS_TDEADR/W0h Insertable digital dead-time.
00b = 0 ns
01b = 2 µs
10b = 4 µs
11b = 8 µs
8RESERVEDR/W0h Reserved
7RESERVEDR/W0h Reserved
6-4VGS_TDRVR/W3h VGS drive time and VDS monitor blanking time.
000b = 2 µs
001b = 4 µs
010b = 8 µs
011b = 12 µs
100b = 16 µs
101b = 24 µs
110b = 32 µs
111b = 96 µs
3VGS_HS_DISR/W0h VGS monitor based dead-time handshake.
0b = Enabled.
1b = Disabled. Gate drive transition based on tDRIVE and tDEAD time duration
2VGS_LVLR/W0h VGS monitor threshold for dead-time handshake and gate fault detection.
0b = 1.4 V
1b = 1.0 V
1-0VGS_MODER/W0h VGS gate fault monitor mode.
00b = Latched fault.
01b = Cycle by cycle.
10b = Warning report only.
11b = Disabled.

8.2.6 GD_VDS_CNFG Register (Offset = Eh) [Reset = 0D2Dh]

GD_VDS_CNFG is shown in Table 8-21.

Return to the Summary Table.

VDS monitoring or short-circuit detection configuration register.

Table 8-21 GD_VDS_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RSVDR/W0h Reserved.
14VDS_INDR/W0h VDS fault independent shutdown mode configuration.
0b = Disabled. VDS fault shuts down all gate drivers.
1b = Enabled. VDS gate fault only shuts down the associated gate driver.
13-12VDS_IDRVNR/W0h IDRVN gate pulldown current after VDS_OCP fault for gate driver 1 and 2.
00b = Programmed IDRVN
01b = 8 mA
10b = 31 mA
11b = 62 mA
11-8VDS_HS_LVLR/WDh High-side VDS overcurrent monitor threshold.
0000b = 0.06 V
00001b = 0.08 V
0010b = 0.10 V
0011b = 0.12 V
0100b = 0.14 V
0101b = 0.16 V
0110b = 0.18 V
0111b = 0.2 V
1000b = 0.3 V
1001b = 0.4 V
1010b = 0.5 V
1011b = 0.6 V
1100b = 0.7 V
1101b = 1 V
1110b = 1.4 V
1111b = 2 V
7-6VDS_MODER/W0h VDS overcurrent monitor mode.
00b = Latched fault.
01b = Cycle by cycle.
10b = Warning report only.
11b = Disabled.
5-4VDS_DGR/W2h VDS overcurrent monitor deglitch time.
00b = 1 µs
01b = 2 µs
10b = 4 µs
11b = 8 µs
3-0VDS_LS_LVLR/WDh Low-side VDS overcurrent monitor threshold.
0000b = 0.06 V
0001b = 0.08 V
0010b = 0.10 V
0011b = 0.12 V
0100b = 0.14 V
0101b = 0.16 V
0110b = 0.18 V
0111b = 0.2 V
1000b = 0.3 V
1001b = 0.4 V
1010b = 0.5 V
1011b = 0.6 V
1100b = 0.7 V
1101b = 1 V
1110b = 1.4 V
1111b = 2 V

8.2.7 GD_CSA_CNFG Register (Offset = Fh) [Reset = 0004h]

GD_CSA_CNFG is shown in Table 8-22.

Return to the Summary Table.

CSA configurations and controls.

Table 8-22 GD_CSA_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7-5CSA_BLKR/W0h Current shunt amplifier blanking time. % of tDRV.
000b = 0 %, Disabled
001b = 25 %
010b = 37.5 %
011b = 50 %
100b = 62.5 %
101b = 75 %
110b = 87.5 %
111b = 100 %
4CSA_BLK_SELR/W0h Current shunt amplifier blanking trigger source.
0b = Gate driver 1
1b = Gate driver 2
3-2CSA_GAINR/W1h Current shunt amplifier gain setting.
00b = 10 V/V
01b = 20 V/V
10b = 40 V/V
11b = 80 V/V
1CSA_DIVR/W0h Current shunt amplifier internal reference voltage divider.
0b = VDVDD / 2
1b = VDVDD/ 8
0CSA_ENR/W0h Current sense amplifier enable.
0b = Disabled
1b = Enabled

8.2.8 GD_AGD_CNFG Register (Offset = 10h) [Reset = 0402h]

GD_AGD_CNFG is shown in Table 8-23.

Return to the Summary Table.

Includes Advanced smart gate driver configurations, enables for DCC and PDR, post-charge settings.

Table 8-23 GD_AGD_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14PDR_ERRR/W0h PDR loop error limit for gate driver 1 and 2.
0b = 1-bit error
1b = Actual error
13-12AGD_ISTRONGR/W0h Adaptive gate driver ISTRONG configuration. 00b = ISTRONG pulldown decoded from initial IDRVP_x register setting.
01b = 62 mA
10b = 124 mA
11b = RSVD
11-10AGD_THRR/W1h Adaptive gate driver VSH threshold configuration.
00b = 0.5V, VDRAIN - 0.5V
01b = 1V, VDRAIN - 1V
10b = 1.5V, VDRAIN - 1.5V
11b = 2V, VDRAIN - 2V
9SET_AGDR/W0h Set active half-bridge for adaptive gate drive control loops.
0b = Gate driver 1
1b = Gate driver 2
8FW_MAXR/W0h Gate drive current used for freewheeling MOSFET for gate driver 1 and 2.
0b = PRE_CHR_MAX_12
1b = 64 mA
7EN_DCCR/W0h Enable duty cycle compensation for half-bridge 1 and 2.
6IDIR_MANR/W0h Current polarity detection mode for half-bridge 1 and 2.
0b = Automatic
1b = Manual (Set by IDIR_MAN_SEL)
5-4KP_PSTR/W0h Post charge proportional control gain setting for half-bridges 1 and 2.
00b = Disabled
01b = 2
10b = 4
11b = 15
3EN_PST_DLYR/W0h Enable post-charge time delay. Time delay is equal to T_DON_DOFF_12 - T_PRE_CHR_12.
2-1KP_PDRR/W1h PDR proportional controller gain setting for half-bridge 1 and 2.
00b = 1
01b = 2
10b = 3
11b = 4
0EN_PDRR/W0h Enable PDR loop control for half-bridge 1 and 2.

8.2.9 GD_PDR_CNFG Register (Offset = 11h) [Reset = 0AF6h]

GD_PDR_CNFG is shown in Table 8-24.

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Includes remaining PDR controls, pre-charge settings and timing.

Table 8-24 GD_PDR_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15-14PRE_MAXR/W0h Maximum gate drive current limit for pre-charge and pre-discharge for half-bridge 1 and 2.
00b = 64 mA
01b = 32 mA
10b = 16 mA
11b = 8 mA
13-8T_DON_DOFFR/WAh On and off time delay for half-bridge 1 and 2. 140 ns x T_DON_DOFF [3:0] Default time: 001010b (1.4 µs)
7-6T_PRE_CHRR/W3h PDR control loop pre-charge time for half-bridge 1 and 2. Set as ratio of T_DON_DOFF_12 [5:0].
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
5-4T_PRE_DCHRR/W3h PDR control loop pre-discharge time for half-bridge 1 and 2. Set as ratio of T_DON_DOFF_12 [5:0].
00b = 1/8
01b = 1/4
10b = 3/8
11b = 1/2
3-2PRE_CHR_INITR/W1h PDR control loop initial pre-charge current setting for half-bridge 1 and 2.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA
1-0PRE_DCHR_INITR/W2h PDR control loop initial pre-discharge current setting for half-bridge 1 and 2.
00b = 4 mA
01b = 8 mA
10b = 16 mA
11b = 32 mA

8.2.10 GD_STC_CNFG Register (Offset = 12h) [Reset = 0026h]

GD_STC_CNFG is shown in Table 8-25.

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Includes configurations and enable for slew time control.

Table 8-25 GD_STC_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8IDIR_MAN_SELR/W0h Manual freewheel selection for Gate Drivers.
0b = High-side MOSFET drive, Low-side MOSFET freewheel.
1b = Low-side MOSFET drive, High-side MOSFET freewheel.
7-4T_RISE_FALLR/W2h Set switch-node VSH rise and fall time for half-bridge 1 and 2.
0000b = 0.35 us
0001b = 0.56 us
0010b = 0.77 us
0011b = 0.98 us
0100b = 1.33 us
0101b = 1.68 us
0110b = 2.03 us
0111b = 2.45 us
1000b = 2.94 us
1001b = 3.99 us
1010b = 4.97 us
1011b = 5.95 us
1100b = 7.98 us
1101b = 9.94 us
1110b = 11.97 us
1111b = 15.96 us
3STC_ERRR/W0h STC loop error limit for half-bridge 1 and 2.
0b = 1-bit error
1b = Actual error
2-1KP_STCR/W3h STC proportional controller gain setting for half-bridge 1 and 2.
00b = 1
01b = 2
10b = 3
11b = 4
0EN_STCR/W0h Enable STC loop control for half-bridge 1 and 2.

8.2.11 GD_SPARE_CNFG1 Register (Offset = 13h) [Reset = 0000h]

GD_SPARE_CNFG1 is shown in Table 8-26.

Return to the Summary Table.

Spare configuration register for gate driver.

Table 8-26 GD_SPARE_CNFG1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3RESERVEDR/W0h Reserved
2RESERVEDR/W0h Reserved
1RESERVEDR/W0h Reserved
0RESERVEDR/W0h Reserved

8.2.12 HB_ITRIP_DG Register (Offset = 14h) [Reset = 0000h]

HB_ITRIP_DG is shown in Table 8-27.

Return to the Summary Table.

Configures ITRIP deglitch for each half-bridge. ITRIP timing is shared between half-bridge pairs.

Table 8-27 HB_ITRIP_DG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11-10OUT6_ITRIP_DGR/W0h Configures ITRIP deglitch time for half-bridge 6.
00b = 2 µs
01b = 5 µs
10b = 10 µs
11b = 20 µs
9-8OUT5_ITRIP_DGR/W0h Configures ITRIP deglitch time for half-bridge 5.
00b = 2 µs
01b = 5 µs
10b = 10 µs
11b = 20 µs
7-6OUT4_ITRIP_DGR/W0h Configures ITRIP deglitch time for half-bridge 4.
00b = 2 µs
01b = 5 µs
10b = 10 µs
11b = 20 µs
5-4OUT3_ITRIP_DGR/W0h Configures ITRIP deglitch time for half-bridge 3.
00b = 2 µs
01b = 5 µs
10b = 10 µs
11b = 20 µs
3-2OUT2_ITRIP_DGR/W0h Configures ITRIP deglitch time for half-bridge 2.
00b = 2 µs
01b = 5 µs
10b = 10 µs
11b = 20 µs
1-0OUT1_ITRIP_DGR/W0h Configures ITRIP deglitch time for half-bridge 1.
00b = 2 µs
01b = 5 µs
10b = 10 µs
11b = 20 µs

8.2.13 HB_OUT_CNFG1 Register (Offset = 15h) [Reset = 0000h]

HB_OUT_CNFG1 is shown in Table 8-28.

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Configures the output mode for each half-bridge, sets IPROPI sample and hold circuit, and half-bridge pair freewheeling.

Table 8-28 HB_OUT_CNFG1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14NSR_OUT6_DISR/W0h Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 6.
Passive freewheeling = 0b
Active freewheeling = 1b
13NSR_OUT5_DISR/W0h Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 5.
Passive freewheeling = 0b
Active freewheeling = 1b
12NSR_OUT4_DISR/W0h Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 4.
Passive freewheeling = 0b
Active freewheeling = 1b
11NSR_OUT3_DISR/W0h Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridges 3.
Passive freewheeling = 0b
Active freewheeling = 1b
10NSR_OUT2_DISR/W0h Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 2.
Passive freewheeling = 0b
Active freewheeling = 1b
9NSR_OUT1_DISR/W0h Disables non-synchronous rectification during ITRIP regulation (sets active freewheeling) for half-bridge 1.
Passive freewheeling = 0b
Active freewheeling = 1b
8IPROPI_SH_ENR/W0h Enables IPROPI sample and hold circuit.
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5-3OUT6_CNFGR/W0h Configuration for half-bridge 6.
Enables or disables control of half-bridge, and sets control mode between PWM or SPI.
000b = Disabled
001b = Enabled (SPI register control)
010b = PWM1 Complementary Control
011b = PWM1 LS Control
100b = PWM1 HS Control
101b = PWM2 Complementary Control
110b = PWM2 LS Control
111b = PWM2 HS Control
2-0OUT5_CNFGR/W0h Configuration for half-bridge 5.
Enables or disables control of half-bridge, and sets control mode between PWM or SPI.
000b = Disabled
001b = Enabled (SPI register control)
010b = PWM1 Complementary Control
011b = PWM1 LS Control
100b = PWM1 HS Control
101b = PWM2 Complementary Control
110b = PWM2 LS Control
111b = PWM2 HS Control

8.2.14 HB_OUT_CNFG2 Register (Offset = 16h) [Reset = 0000h]

HB_OUT_CNFG2 is shown in Table 8-29.

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Configures the output mode for each half-bridge.

Table 8-29 HB_OUT_CNFG2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13-11OUT4_CNFGR/W0h Configuration for half-bridge 4.
Enables or disables control of half-bridge, and sets control mode between PWM or SPI.
000b = Disabled
001b = Enabled (SPI register control)
010b = PWM1 Complementary Control
011b = PWM1 LS Control
100b = PWM1 HS Control
101b = PWM2 Complementary Control
110b = PWM2 LS Control
111b = PWM2 HS Control
10-8OUT3_CNFGR/W0h Configuration for half-bridge 3.
Enables or disables control of half-bridge, and sets control mode between PWM or SPI.
000b = Disabled
001b = Enabled (SPI register control)
010b = PWM1 Complementary Control
011b = PWM1 LS Control
100b = PWM1 HS Control
101b = PWM2 Complementary Control
110b = PWM2 LS Control
111b = PWM2 HS Control
7OUT2_MODER/W0h Bit to enable OUT2 as High Side driver with internal PWM.
OUT2_CNFG used for enabling and disabling the driver
PWM settings - Freq: PWM_OUT2_FREQ, DC: OUT2_DC.
6OUT1_MODER/W0h Bit to enable OUT1 as High Side driver with internal PWM.
OUT1_CNFG used for enabling and disabling the driver
PWM settings - Freq: PWM_OUT1_FREQ, DC: OUT1_DC.
5-3OUT2_CNFGR/W0h Configuration for half-bridge 2.
Enables or disables control of half-bridge, and sets control mode between PWM or SPI.
000b = Disabled
001b = Enabled (SPI register control)
010b = PWM1 Complementary Control
011b = PWM1 LS Control
100b = PWM1 HS Control
101b = PWM2 Complementary Control
110b = PWM2 LS Control
111b = PWM2 HS Control
2-0OUT1_CNFGR/W0h Configuration for half-bridge 1.
Enables or disables control of half-bridge, and sets control mode between PWM or SPI.
000b = Disabled
001b = Enabled (SPI register control)
010b = PWM1 Complementary Control
011b = PWM1 LS Control
100b = PWM1 HS Control
101b = PWM2 Complementary Control
110b = PWM2 LS Control
111b = PWM2 HS Control

8.2.15 HB_OCP_CNFG Register (Offset = 17h) [Reset = 0000h]

HB_OCP_CNFG is shown in Table 8-30.

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Overcurrent deglitch for half-bridges configuration register.

Table 8-30 HB_OCP_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11-10OUT6_OCP_DGR/W0h Overcurrent deglitch time for half-bridge 6.
00b = 6 µs
01b = 10 µs
10b = 15 µs
11b = 60 µs
9-8OUT5_OCP_DGR/W0h Overcurrent deglitch time for half-bridge 5.
00b = 6 µs
01b = 10 µs
10b = 15 µs
11b = 60 µs
7-6OUT4_OCP_DGR/W0h Overcurrent deglitch time for half-bridge 4.
00b = 6 µs
01b = 10 µs
10b = 15 µs
11b = 60 µs
5-4OUT3_OCP_DGR/W0h Overcurrent deglitch time for half-bridge 3.
00b = 6 µs
01b = 10 µs
10b = 15 µs
11b = 60 µs
3-2OUT2_OCP_DGR/W0h Overcurrent deglitch time for half-bridge 2.
00b = 6 µs
01b = 10 µs
10b = 15 µs
11b = 60 µs
1-0OUT1_OCP_DGR/W0h Overcurrent deglitch time for half-bridge 1.
00b = 6 µs
01b = 10 µs
10b = 15 µs
11b = 60 µs

8.2.16 HB_OL_CNFG1 Register (Offset = 18h) [Reset = 0000h]

HB_OL_CNFG1 is shown in Table 8-31.

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Configures active and off-state open load detection circuits for half-bridges.

Table 8-31 HB_OL_CNFG1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13-12HB_OLP_CNFGR/W0h Off-state diagnostics configuration.
00b = Off-state disabled
01b = OUT X Pullup enabled, OUT Y pulldown enabled, OUT Y selected, VREF Low
10b = OUT X Pullup enabled, OUT Y pulldown enabled, OUT X selected, VREF High
11b = OUT X Pulldown enabled, OUT Y pullup enabled, OUT Y selected, VREF Low
11-8HB_OLP_SELR/W0h Off-state open load diagnostics enable for half-bridges.
0000b = Disabled
0001b = OUT1 and OUT2
0010b = OUT1 and OUT3
0011b = OUT1 and OUT4
0100b = OUT1 and OUT5
0101b = OUT1 and OUT6
0110b = OUT2 and OUT3
0111b = OUT2 and OUT4
1000b = OUT2 and OUT5
1001b = OUT2 and OUT6
1010b = OUT3 and OUT4
1011b = OUT3 and OUT5
1100b = OUT3 and OUT6
1101b = OUT4 and OUT5
1110b = OUT4 and OUT6
1111b = OUT5 and OUT6
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5OUT6_OLA_ENR/W0h Active open load diagnostics enable for half-bridge 6.
0b = Disabled
1b = Enabled
4OUT5_OLA_ENR/W0h Active open load diagnostics enable for half-bridge 5.
0b = Disabled
1b = Enabled
3OUT4_OLA_ENR/W0h Active open load diagnostics enable for half-bridge 4.
0b = Disabled
1b = Enabled
2OUT3_OLA_ENR/W0h Active open load diagnostics enable for half-bridge 3.
0b = Disabled
1b = Enabled
1OUT2_OLA_ENR/W0h Active open load diagnostics enable for half-bridge 2.
0b = Disabled
1b = Enabled
0OUT1_OLA_ENR/W0h Active open load diagnostics enable for half-bridge 1.
0b = Disabled
1b = Enabled

8.2.17 HB_OL_CNFG2 Register (Offset = 19h) [Reset = 0000h]

HB_OL_CNFG2 is shown in Table 8-32.

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Configures cycle count threshold for active open load detection circuits of half-bridges.

Table 8-32 HB_OL_CNFG2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11-10OUT6_OLA_THR/W0h Sets the half-bridge 6 active open load cycle count threshold.
0b = 32 cycles
1b = 128 cycles
10b - 512 cycles
11b - 1024 cycles
9-8OUT5_OLA_THR/W0h Sets the half-bridge 5 active open load cycle count threshold.
0b = 32 cycles
1b = 128 cycles
10b - 512 cycles
11b - 1024 cycles
7-6OUT4_OLA_THR/W0h Sets the half-bridge 4 active open load cycle count threshold.
0b = 32 cycles
1b = 128 cycles
10b - 512 cycles
11b - 1024 cycles
5-4OUT3_OLA_THR/W0h Sets the half-bridge 3 active open load cycle count threshold.
0b = 32 cycles
1b = 128 cycles
10b - 512 cycles
11b - 1024 cycles
3-2OUT2_OLA_THR/W0h Sets the half-bridge 2 active open load cycle count threshold.
0b = 32 cycles
1b = 128 cycles
10b - 512 cycles
11b - 1024 cycles
1-0OUT1_OLA_THR/W0h Sets the half-bridge 1 active open load cycle count threshold.
0b = 32 cycles
1b = 128 cycles
10b - 512 cycles
11b - 1024 cycles

8.2.18 HB_SR_CNFG Register (Offset = 1Ah) [Reset = 0000h]

HB_SR_CNFG is shown in Table 8-33.

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Configures slew rate timing for each half-bridge.

Table 8-33 HB_SR_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11-10OUT6_SRR/W0h Configures slew rate for half-bridge 6.
00b = 1.6 V/µs
01b = 13.5 V/µs
10b = 24 V/µs
9-8OUT5_SRR/W0h Configures slew rate for half-bridge 5.
00b = 1.6 V/µs
01b = 13.5 V/µs
10b = 24 V/µs
7-6OUT4_SRR/W0h Configures slew rate for half-bridge 4.
00b = 1.6 V/µs
01b = 13.5 V/µs
10b = 24 V/µs
5-4OUT3_SRR/W0h Configures slew rate for half-bridge 3.
00b = 1.6 V/µs
01b = 13.5 V/µs
10b = 24 V/µs
3-2OUT2_SRR/W0h Configures slew rate for half-bridge 2.
00b = 1.6 V/µs
01b = 13.5 V/µs
10b = 24 V/µs
1-0OUT1_SRR/W0h Configures slew rate for half-bridge 1.
00b = 1.6 V/µs
01b = 13.5 V/µs
10b = 24 V/µs

8.2.19 HB_ITRIP_CNFG Register (Offset = 1Bh) [Reset = 0000h]

HB_ITRIP_CNFG is shown in Table 8-34.

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Configures ITRIP levels and enables ITRIP for each half-bridge. ITRIP levels are shared between half-bridge pairs.

Table 8-34 HB_ITRIP_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15OUT6_ITRIP_ENR/W0h Enables ITRIP regulation for half-bridge 6.
14OUT5_ITRIP_ENR/W0h Enables ITRIP regulation for half-bridge 5.
13OUT4_ITRIP_ENR/W0h Enables ITRIP regulation for half-bridge 4.
12OUT3_ITRIP_ENR/W0h Enables ITRIP regulation for half-bridge 3.
11OUT2_ITRIP_ENR/W0h Enables ITRIP regulation for half-bridge 2.
10OUT1_ITRIP_ENR/W0h Enables ITRIP regulation for half-bridge 1.
9-8OUT6_ITRIP_LVLR/W0h Configures ITRIP current threshold level for half-bridge 6.
00b = 2.3 A.
01b = 5.4 A
10b = 6.2 A
11b = Reserved.
7-6OUT5_ITRIP_LVLR/W0h Configures ITRIP current threshold level for half-bridge 5.
00b = 2.9 A
01b = 6.6 A
10b = 7.6 A
11b = Reserved.
5-4OUT4_ITRIP_LVLR/W0h Configures ITRIP current threshold level for half-bridge 4.
00b = 1.3 A
01b = 2.5 A
10b = 3.4 A
11b = Reserved.
3-2OUT3_ITRIP_LVLR/W0h Configures ITRIP current threshold level for half-bridge 3.
00b = 1.3 A
01b = 2.5 A
10b = 3.4 A
11b = Reserved.
1OUT2_ITRIP_LVLR/W0h Configures ITRIP current threshold level for half-bridge 2.
0b = 0.7 A
1b = 0.875 A
0OUT1_ITRIP_LVLR/W0h Configures ITRIP current threshold level for half-bridge 1.
0b = 0.7 A
1b = 0.875 A

8.2.20 HB_ITRIP_FREQ Register (Offset = 1Ch) [Reset = 0000h]

HB_ITRIP_FREQ is shown in Table 8-35.

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Configures ITRIP frequency and deglitch for each half-bridge. ITRIP timing is shared between half-bridge pairs.

Table 8-35 HB_ITRIP_FREQ Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13-12HB_TOFF_SELR/W0h Toff selection for OUT1-6 half bridge drivers. Here T is decided by OUTx_ITRIP_FREQ.
00b - Zero, disabled
01b - Toff = T/2
10b - Toff=T/4
11b - Toff=T
11-10OUT6_ITRIP_FREQR/W0h Configures ITRIP regulation frequency for half-bridge 6.
00b = 20 kHz
01b = 10 kHz
10b = 5 kHz
11b = 2.5 kHz
9-8OUT5_ITRIP_FREQR/W0h Configures ITRIP regulation frequency for half-bridge 5.
00b = 20 kHz
01b = 10 kHz
10b = 5 kHz
11b = 2.5 kHz
7-6OUT4_ITRIP_FREQR/W0h Configures ITRIP regulation frequency for half-bridge 4. 00b = 20 kHz
01b = 10 kHz
10b = 5 kHz
11b = 2.5 kHz
5-4OUT3_ITRIP_FREQR/W0h Configures ITRIP regulation frequency for half-bridge 3.
00b = 20 kHz
01b = 10 kHz
10b = 5 kHz
11b = 2.5 kHz
3-2OUT2_ITRIP_FREQ/PWM_OUT2_FREQR/W0h Configures ITRIP regulation frequency for half-bridge 2.
00b = 20 kHz
01b = 10 kHz
10b = 5 kHz
11b = 2.5 kHz
When OUT2_MODE = 1. Used for PWM FREQ settings PWM_OUT2_FREQ:
00b - 108Hz
01b - 217Hz
10b - 289Hz
11b - 434Hz
1-0OUT1_ITRIP_FREQ/PWM_OUT1_FREQR/W0h Configures ITRIP regulation frequency for half-bridge 1.
00b = 20 kHz
01b = 10 kHz
10b = 5 kHz
11b = 2.5 kHz
When OUT1_MODE = 1. Used for PWM FREQ settings PWM_OUT1_FREQ:
00b - 108Hz
01b - 217Hz
10b - 289Hz
11b - 434Hz

8.2.21 HS_HEAT_OUT_CNFG Register (Offset = 1Dh) [Reset = 0000h]

HS_HEAT_OUT_CNFG is shown in Table 8-36.

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Configures the output mode for each high-side driver and heater.

Table 8-36 HS_HEAT_OUT_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15-14HEAT_CNFGR/W0h Configuration for heater driver. Enables or disables control of heater, and sets control mode between PWM or SPI.
00b = Disabled
01b = SPI control enabled
10b = PWM1 pin control
11b = Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11-10OUT12_CNFGR/W0h Configuration for high-side driver 12. Enables or disables control of high-side driver, and sets control mode between PWM or SPI.
00b = Disabled
01b = SPI control enabled
10b = PWM pin control
11b = PWM Generator
9-8OUT11_CNFGR/W0h Configuration for high-side driver 11. Enables or disables control of high-side driver, and sets control mode between PWM or SPI.
00b = Disabled
01b = SPI control enabled
10b = PWM pin control
11b = PWM Generator
7-6OUT10_CNFGR/W0h Configuration for high-side driver 10. Enables or disables control of high-side driver, and sets control mode between PWM or SPI.
00b = Disabled
01b = SPI control enabled
10b = PWM pin control
11b = PWM Generator
5-4OUT9_CNFGR/W0h Configuration for high-side driver 9. Enables or disables control of high-side driver, and sets control mode between PWM or SPI.
00b = Disabled
01b = SPI control enabled
10b = PWM pin control
11b = PWM Generator
3-2OUT8_CNFGR/W0h Configuration for high-side driver 8. Enables or disables control of high-side driver, and sets control mode between PWM or SPI.
00b = Disabled
01b = SPI control enabled
10b = PWM pin control
11b = PWM Generator
1-0OUT7_CNFGR/W0h Configuration for high-side driver 7. Enables or disables control of high-side driver, and sets control mode between PWM or SPI.
00b = Disabled
01b = SPI control enabled
10b = PWM pin control
11b = PWM Generator

8.2.22 HS_OC_CNFG Register (Offset = 1Eh) [Reset = 1000h]

HS_OC_CNFG is shown in Table 8-37.

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Configures overcurrent threshold for each high-side driver.

Table 8-37 HS_OC_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12OUT11_EC_MODER/W1h Bit sets high-side OUT11 for independent control through OUT11_CNFG bits or for supply for Electrochromic dirver.
0b = OUT11 is configured as independent high-side driver. Drain of EC FET is connected to PVDD
1b = OUT11 is configured as supply for EC FET
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5OUT12_OC_THR/W0h Configures overcurrent threshold between high or low for high-side driver 12.
0b = Low current threshold
1b = High current threshold
4OUT11_OC_THR/W0h Configures overcurrent threshold between high or low for high-side driver 11.
0b = Low current threshold
1b = High current threshold
3OUT10_OC_THR/W0h Configures overcurrent threshold between high or low for high-side driver 10.
0b = Low current threshold
1b = High current threshold
2OUT9_OC_THR/W0h Configures overcurrent threshold between high or low for high-side driver 9.
0b = Low current threshold
1b = High current threshold
1OUT8_OC_THR/W0h Configures overcurrent threshold between high or low for high-side driver 8.
0b = Low current threshold
1b = High current threshold
0OUT7_RDSON_MODER/W0h Configures high-side driver 7 between high RDSON mode and low RDSON mode (for bulb/lamp load).
0b = High RDSON mode (LED driver mode)
1b = Low RDSON mode (bulb/lamp driver mode)

8.2.23 HS_OL_CNFG Register (Offset = 1Fh) [Reset = 0000h]

HS_OL_CNFG is shown in Table 8-38.

Return to the Summary Table.

Configures open load threshold for each high-side driver.

Table 8-38 HS_OL_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13OUT12_OLA_THR/W0h Configures high-side driver 12 open load threshold.
0b = Low threshold
1b = High threshold
12OUT11_OLA_THR/W0h Configures high-side driver 11 open load threshold.
0b = Low threshold
1b = High threshold
11OUT10_OLA_THR/W0h Configures high-side driver 10 open load threshold.
0b = Low threshold
1b = High threshold
10OUT9_OLA_THR/W0h Configures high-side driver 9 open load threshold.
0b = Low threshold
1b = High threshold
9OUT8_OLA_THR/W0h Configures high-side driver 8 open load threshold.
0b = Low threshold
1b = High threshold
8RESERVEDR/W0h Reserved
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5OUT12_OLA_ENR/W0h Enables open load detection circuit for high-side driver 12.
4OUT11_OLA_ENR/W0h Enables open load detection circuit for high-side driver 11.
3OUT10_OLA_ENR/W0h Enables open load detection circuit for high-side driver 10.
2OUT9_OLA_ENR/W0h Enables open load detection circuit for high-side driver 9.
1OUT8_OLA_ENR/W0h Enables open load detection circuit for high-side driver 8.
0OUT7_OLA_ENR/W0h Enables open load detection circuit for high-side driver 7.

8.2.24 HS_REG_CNFG1 Register (Offset = 20h) [Reset = 0000h]

HS_REG_CNFG1 is shown in Table 8-39.

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Configures OUT7 ITRIP settings.

Table 8-39 HS_REG_CNFG1 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7OUT7_ITRIP_ENR/W0h Enables ITRIP for high-side driver 7.
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3-2OUT7_ITRIP_FREQR/W0h Configures OUT7 ITRIP regulation frequency.
00b = 1.7 kHz
01b = 2.2 kHz
10b = 3 kHz
11b = 4.4 kHz
1-0OUT7_ITRIP_DGR/W0h Configures OUT7 ITRIP deglitch time.
00b = 48 µs
01b = 40 µs
10b = 32 µs
11b = 24 µs

8.2.25 HS_REG_CNFG2 Register (Offset = 21h) [Reset = 0000h]

HS_REG_CNFG2 is shown in Table 8-40.

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Configures constant current mode for each high-side driver.

Table 8-40 HS_REG_CNFG2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13OUT12_CCM_TOR/W0h Configures the constant current mode current limit option of high-side output 12.
0b = 350 mA
1b = 450 mA
12OUT11_CCM_TOR/W0h Configures the constant current mode current limit option of high-side output 11.
0b = 350 mA
1b = 450 mA
11OUT10_CCM_TOR/W0h Configures the constant current mode current limit option of high-side output 10.
0b = 350 mA
1b = 450 mA
10OUT9_CCM_TOR/W0h Configures the constant current mode current limit option of high-side output 9.
0b = 350 mA
1b = 450 mA
9OUT8_CCM_TOR/W0h Configures the constant current mode current limit option of high-side output 8.
0b = 350 mA
1b = 450 mA
8OUT7_CCM_TOR/W0h Configures the constant current mode current limit option of high-side output 7. CCM values are based on OUT7_RDSON_MODE.
If OUT7_RDSON_MODE = 0b:
0b = 250 mA
1b = 330 mA

IF OUT7_RDSON_MODE = 1b:
0b = 360 mA 1b = 450 mA
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5OUT12_CCM_ENR/W0h Enables constant current mode circuit for high-side driver 12.
4OUT11_CCM_ENR/W0h Enables constant current mode circuit for high-side driver 11.
3OUT10_CCM_ENR/W0h Enables constant current mode circuit for high-side driver 10.
2OUT9_CCM_ENR/W0h Enables constant current mode circuit for high-side driver 9.
1OUT8_CCM_ENR/W0h Enables constant current mode circuit for high-side driver 8.
0OUT7_CCM_ENR/W0h Enables constant current mode circuit for high-side driver 7.

8.2.26 HS_PWM_FREQ_CNFG Register (Offset = 22h) [Reset = 0000h]

HS_PWM_FREQ_CNFG is shown in Table 8-41.

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Configures the frequency for each dedicated PWM generator.

Table 8-41 HS_PWM_FREQ_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11-10PWM_OUT12_FREQR/W0h Configures frequency output of dedicated PWM generator for high-side driver 12.
00b = 108 Hz
01b = 217 Hz
10b = 289 Hz
11b = 434 Hz
9-8PWM_OUT11_FREQR/W0h Configures frequency output of dedicated PWM generator for high-side driver 11.
00b = 108 Hz
01b = 217 Hz
10b = 289 Hz
11b = 434 Hz
7-6PWM_OUT10_FREQR/W0h Configures frequency output of dedicated PWM generator for high-side driver 10.
00b = 108 Hz
01b = 217 Hz
10b = 289 Hz
11b = 434 Hz
5-4PWM_OUT9_FREQR/W0h Configures frequency output of dedicated PWM generator for high-side driver 9.
00b = 108 Hz
01b = 217 Hz
10b = 289 Hz
11b = 434 Hz
3-2PWM_OUT8_FREQR/W0h Configures frequency output of dedicated PWM generator for high-side driver 8.
00b = 108 Hz
01b = 217 Hz
10b = 289 Hz
11b = 434 Hz
1-0PWM_OUT7_FREQR/W0h Configures frequency output of dedicated PWM generator for high-side driver 7.
00b = 108 Hz
01b = 217 Hz
10b = 289 Hz
11b = 434 Hz

8.2.27 HEAT_CNFG Register (Offset = 23h) [Reset = 0A3Ch]

HEAT_CNFG is shown in Table 8-42.

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Configures heater driver and fault responses.

Table 8-42 HEAT_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11-8HEAT_VDS_LVLR/WAh Heater MOSFET VDS monitor protection threshold.
0000b = 0.06 V
00001b = 0.08 V
0010b = 0.10 V
0011b = 0.12 V
0100b = 0.14 V
0101b = 0.16 V
0110b = 0.18 V
0111b = 0.2 V
1000b = 0.24 V
1001b = 0.28 V
1010b = 0.32 V
1011b = 0.36 V
1100b = 0.4 V
1101b = 0.44 V
1110b = 0.56 V
1111b = 1 V
7-6HEAT_VDS_MODER/W0h Heater MOSFET VDS overcurrent monitor fault mode.
00b = Latched fault.
01b = Cycle by cycle.
10b = Warning report only.
11b = Disabled.
5-4HEAT_VDS_BLKR/W3h Heater MOSFET VDS monitor blanking time.
00b = 4 µs
01b = 8 µs
10b = 16 µs
11b = 32 µs
3-2HEAT_VDS_DGR/W3h Heater MOSFET VDS overcurrent monitor deglitch time.
00b = 1 µs
01b = 2 µs
10b = 4 µs
11b = 8 µs
1HEAT_OLP_ENR/W0h Enables heater offline open load detection circuit.
0RESERVEDR/W0h Reserved

8.2.28 EC_CNFG Register (Offset = 24h) [Reset = 0000h]

EC_CNFG is shown in Table 8-43.

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Configures electrochrome driver and fault responses.

Table 8-43 EC_CNFG Register Field Descriptions
BitFieldTypeResetDescription
15-14ECFB_DIAGR/W0h Enables open-load detection circuit on ECFB.
00b = disable
01b = SC
10b = OLP
11b = disable/reserved
13-12EC_OUT11_OCP_DGR/W0h OUT11 OCP Deglitch setting when EC_MODE=1
00b = 6 µs
01b = 10 µs
10b = 15 µs
11b = 60 µs
11-10ECFB_SC_RSELR/W0h ECFB Diagnostic short-circuit detection options.
00b = 0.5 Ω
01b = 1.0 Ω
10b = 2.0 Ω
11b = 3.0 Ω
9-8ECFB_OV_DGR/W0h Configures overvoltage fault deglitch time. 00b = 20 µs
01b = 50 µs
10b = 100 µs
11b = 200 µs
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5-4ECFB_OV_MODER/W0h Configures ECFB OV fault response for EC driver.
0b = No action
01b = Report ECFB_OV if voltage > 3V longer than EFB_OV_DG time.
10b = Report ECFB_OV if voltage > 3V longer than EFB_OV_DG time, drive ECDRV low with pulldown.
3EC_FLT_MODER/W0h Configures overcurrent fault response for EC driver.
0b = Hi-Z EC Driver
1b = Retry with OUT7 ITRIP settings
2ECFB_LS_PWMR/W0h Enables LS PWM discharge for EC load.
0b = No PWM discharge (Fast discharge)
1b = PWM discharge enabled
1EC_OLENR/W0h This bit enables the open load detection circuit during EC discharge.
0b = Open load detection disabled during EC discharge
1b = Open load detection enabled during EC discharge
0ECFB_MAXR/W0h Configures the maximum target voltage for EC.
0b = 1.2 V
1b = 1.5 V

8.2.29 HS_REG_CNFG3 Register (Offset = 25h) [Reset = 0000h]

HS_REG_CNFG3 is shown in Table 8-44.

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Configures HS ITRIP settings.

Table 8-44 HS_REG_CNFG3 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11-10HS_OUT_ITRIP_FREQR/W0h ITRIP FREQ settings for OUT8-12
00b - 1.7KHz
01b - 2.2KHz
10b - 3KHz
11b - 4.4KHz
9-8HS_OUT_ITRIP_DGR/W0h Common ITRIP deglitch settings for OUT8-12 drivers
00b - 48 µs
01b - 40 µs
10b - 32 µs
11b - 24 µs
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4HS_OUT12_ITRIP_ENR/W0h Enables ITRIP for high-side driver 12.
3HS_OUT11_ITRIP_ENR/W0h Enables ITRIP for high-side driver 11.
2HS_OUT10_ITRIP_ENR/W0h Enables ITRIP for high-side driver 10.
1HS_OUT9_ITRIP_ENR/W0h Enables ITRIP for high-side driver 9.
0HS_OUT8_ITRIP_ENR/W0h Enables ITRIP for high-side driver 8.

8.2.30 SPARE_CNFG2 Register (Offset = 26h) [Reset = 0000h]

SPARE_CNFG2 is shown in Table 8-45.

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Spare configuration register.

Table 8-45 SPARE_CNFG2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9RESERVEDR/W0h Reserved
8RESERVEDR/W0h Reserved
7RESERVEDR/W0h Reserved
6RESERVEDR/W0h Reserved
5RESERVEDR/W0h Reserved
4RESERVEDR/W0h Reserved
3RESERVEDR/W0h Reserved
2RESERVEDR/W0h Reserved
1RESERVEDR/W0h Reserved
0RESERVEDR/W0h Reserved

8.2.31 OUT1_HS_MODE_DC Register (Offset = 27h) [Reset = 0000h]

OUT1_HS_MODE_DC is shown in Table 8-46.

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Configures 10 bits for duty cycle

Table 8-46 OUT1_HS_MODE_DC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9-0OUT1_DCR/W0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for OUT1 with max value of 1022 when OUT1_MODE=1.

8.2.32 OUT2_HS_MODE_DC Register (Offset = 28h) [Reset = 0000h]

OUT2_HS_MODE_DC is shown in Table 8-47.

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Configures 10 bits for duty cycle

Table 8-47 OUT2_HS_MODE_DC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9-0OUT2_DCR/W0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for OUT2 with max value of 1022 when OUT2_MODE=1.