SLVSH22A May   2024  – September 2025 DRV8000-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUTx HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Short-circuit Protection
          3. 7.4.2.2.3 High-side Driver Overcurrent Protection
          4. 7.4.2.2.4 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.4.3 Half-bridge Register Control
        4. 7.4.4.4 Half-Bridge ITRIP Regulation
        5. 7.4.4.5 Half-bridge Protection and Diagnostics
          1. 7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.5.2 Half-bridge Open Load Detection
          3. 7.4.4.5.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short-circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IDRIVE Calculation Example
        2. 9.2.2.2 tDRIVE Calculation Example
        3. 9.2.2.3 Maximum PWM Switching Frequency
        4. 9.2.2.4 Current Shunt Amplifier Configuration
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Pre-Production Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

8.3 DRV8000-Q1_CTRL Registers

Table 8-48 lists the memory-mapped registers for the DRV8000-Q1_CTRL registers. All register offset addresses not listed in Table 8-48 should be considered as reserved locations and the register contents should not be modified.

Table 8-48 DRV8000-Q1_CTRL Registers
OffsetAcronymRegister NameSection
29hIC_CTRLIC control register.Section 8.3.1
2AhGD_HB_CTRLGate driver and half-bridge control register.Section 8.3.2
2BhHS_EC_HEAT_CTRLHigh-side driver, EC, and heater driver control register.Section 8.3.3
2ChOUT7_PWM_DCOUT7 PWM Duty cycle control register.Section 8.3.4
2DhOUT8_PWM_DCOUT8 PWM Duty cycle control register.Section 8.3.5
2EhOUT9_PWM_DCOUT9 PWM Duty cycle control register.Section 8.3.6
2FhOUT10_PWM_DCOUT10 PWM Duty cycle control register.Section 8.3.7
30hOUT11_PWM_DCOUT11 PWM Duty cycle control register.Section 8.3.8
31hOUT12_PWM_DCOUT12 PWM Duty cycle control register.Section 8.3.9

Complex bit access types are encoded to fit into small table cells. Table 8-49 shows the codes that are used for access types in this section.

Table 8-49 DRV8000-Q1_CTRL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.1 IC_CTRL Register (Offset = 29h) [Reset = 006Ch]

IC_CTRL is shown in Table 8-50.

Return to the Summary Table.

Control register to lock and unlock configuration or control registers, and clear faults.

Table 8-50 IC_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13IPROPI_MODER/W0h Selects IPROPI/PWM2 pin mode between input and output modes.
0b = Output (IPROPI mode)
1b = Input (PWM mode)
12-8IPROPI_SELR/W0h Controls IPROPI MUX output between current, voltage, and temperature sense output.
00000b = No output
00001b = OUT1 current sense output
00010b = OUT2 current sense output
00011b = OUT3 current sense output
00100b = OUT4 current sense output
00101b = OUT5 current sense output
00110b = OUT6 current sense output
00111b = OUT7 current sense output
01000b = OUT8 current sense output
01001b = OUT9 current sense output
01010b = OUT10 current sense output
01011b = OUT11 current sense output
01100b = OUT12 current sense output
01101b = Reserved.
01110b = Reserved.
01111b = Reserved.
10000b = VPVDD Sense Nominal Range (5V -22V)
10001b = Thermal cluster 1 output
10010b = Thermal cluster 2 output
10011b = Thermal cluster 3 output
10100b = Thermal cluster 4 output
10101b = VPVDD Sense High Range (20V - 32V)
7-5CTRL_LOCKR/W3h Lock and unlock the control registers. Bit settings not listed have no effect.
011b = Unlock all control registers.
110b = Lock the control registers by ignoring further writes except to the IC_CTRL register.
4-2CNFG_LOCKR/W3h Lock and unlock the configuration registers. Bit settings not listed have no effect.
011b = Unlock all configuration registers.
110b = Lock the configuration registers by ignoring further writes.
1WD_RSTR/W0h Watchdog restart.
0b by default after power up.
Invert this bit to restart the watchdog timer.
After written, the bit reflects the new inverted value.
0CLR_FLTR/W0h Clear latched fault status information.
0b = Default state.
1b = Clear latched fault bits, resets to 0b after completion. It also clears SPI fault and watchdog fault status.

8.3.2 GD_HB_CTRL Register (Offset = 2Ah) [Reset = 0000h]

GD_HB_CTRL is shown in Table 8-51.

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Gate driver and half-bridge output control register.

Table 8-51 GD_HB_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15S_HIZ2R/W0h Gate driver 2 Hi-Z control bit.
Active only in half-bridge input control mode.
0b = Outputs follow GD_IN2 signal.
1b = Gate drivers ISTRONG pulldowns are enabled. Half-bridge 2 Hi-Z
14S_HIZ1R/W0h Gate driver 1 Hi-Z control bit.
Active only in half-bridge input control mode.
0b = Outputs follow GD_IN1 signal.
1b = Gate drivers ISTRONG pulldowns are enabled. Half-bridge 1 Hi-Z
13S_IN2R/W0h Register control bit alternative to GD_IN2 input pin signal.
Enabled through IN2_MODE bit.
12S_IN1R/W0h Register control bit alternative to GD_IN1 input pin signal.
Enabled through IN1_MODE bit.
11-10OUT6_CTRLR/W0h Integrated half-bridge output 6 control.
00b = OFF
01b = HS ON
10b = LS ON
11b = RSVD
9-8OUT5_CTRLR/W0h Integrated half-bridge output 5 control.
00b = OFF
01b = HS ON
10b = LS ON
11b = RSVD
7-6OUT4_CTRLR/W0h Integrated half-bridge output 4 control.
00b = OFF
01b = HS ON
10b = LS ON
11b = RSVD
5-4OUT3_CTRLR/W0h Integrated half-bridge output 3 control.
00b = OFF
01b = HS ON
10b = LS ON
11b = RSVD
3-2OUT2_CTRLR/W0h Integrated half-bridge output 2 control.
00b = OFF
01b = HS ON
10b = LS ON
11b = RSVD
1-0OUT1_CTRLR/W0h Integrated half-bridge output 1 control.
00b = OFF
01b = HS ON
10b = LS ON
11b = RSVD

8.3.3 HS_EC_HEAT_CTRL Register (Offset = 2Bh) [Reset = 0000h]

HS_EC_HEAT_CTRL is shown in Table 8-52.

Return to the Summary Table.

High-side driver, EC, and heater driver output control register.

Table 8-52 HS_EC_HEAT_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15ECFB_LS_ENR/W0h Enables EC discharge with LS MOSFET on ECFB while the EC regulation is active.
14EC_ONR/W0h Enables the EC output.
13-8EC_V_TARR/W0h 6-bits of resolution to control the target voltage on ECFB. 0 V to ECFB max (1.2 or 1.5V).
7HEAT_ENR/W0h Enables heater output.
6RESERVEDR/W0h Reserved
5OUT12_ENR/W0h Enables high-side driver 12.
4OUT11_ENR/W0h Enables high-side driver 11.
3OUT10_ENR/W0h Enables high-side driver 10.
2OUT9_ENR/W0h Enables high-side driver 9.
1OUT8_ENR/W0h Enables high-side driver 8.
0OUT7_ENR/W0h Enables high-side driver 7.

8.3.4 OUT7_PWM_DC Register (Offset = 2Ch) [Reset = 0000h]

OUT7_PWM_DC is shown in Table 8-53.

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10-bit duty cycle control for high-side driver 7.

Table 8-53 OUT7_PWM_DC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9-0OUT7_DCR/W0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 7 with max value of 1022.

8.3.5 OUT8_PWM_DC Register (Offset = 2Dh) [Reset = 0000h]

OUT8_PWM_DC is shown in Table 8-54.

Return to the Summary Table.

10-bit duty cycle control for high-side driver 8.

Table 8-54 OUT8_PWM_DC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9-0OUT8_DCR/W0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 8 with max value of 1022.

8.3.6 OUT9_PWM_DC Register (Offset = 2Eh) [Reset = 0000h]

OUT9_PWM_DC is shown in Table 8-55.

Return to the Summary Table.

10-bit duty cycle control for high-side driver 9.

Table 8-55 OUT9_PWM_DC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9-0OUT9_DCR/W0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 9 with max value of 1022.

8.3.7 OUT10_PWM_DC Register (Offset = 2Fh) [Reset = 0000h]

OUT10_PWM_DC is shown in Table 8-56.

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10-bit duty cycle control for high-side driver 10.

Table 8-56 OUT10_PWM_DC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9-0OUT10_DCR/W0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 10 with max value of 1022.

8.3.8 OUT11_PWM_DC Register (Offset = 30h) [Reset = 0000h]

OUT11_PWM_DC is shown in Table 8-57.

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10-bit duty cycle control for high-side driver 11.

Table 8-57 OUT11_PWM_DC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9-0OUT11_DCR/W0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 11 with max value of 1022.

8.3.9 OUT12_PWM_DC Register (Offset = 31h) [Reset = 0000h]

OUT12_PWM_DC is shown in Table 8-58.

Return to the Summary Table.

10-bit duty cycle control for high-side driver 12.

Table 8-58 OUT12_PWM_DC Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0h Reserved
14RESERVEDR/W0h Reserved
13RESERVEDR/W0h Reserved
12RESERVEDR/W0h Reserved
11RESERVEDR/W0h Reserved
10RESERVEDR/W0h Reserved
9-0OUT12_DCR/W0h 10-bit resolution control of Duty Cycle for dedicated PWM generator for high-side driver 12 with max value of 1022.