SLVSH22A May   2024  – September 2025 DRV8000-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUTx HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Short-circuit Protection
          3. 7.4.2.2.3 High-side Driver Overcurrent Protection
          4. 7.4.2.2.4 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.4.3 Half-bridge Register Control
        4. 7.4.4.4 Half-Bridge ITRIP Regulation
        5. 7.4.4.5 Half-bridge Protection and Diagnostics
          1. 7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.5.2 Half-bridge Open Load Detection
          3. 7.4.4.5.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short-circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IDRIVE Calculation Example
        2. 9.2.2.2 tDRIVE Calculation Example
        3. 9.2.2.3 Maximum PWM Switching Frequency
        4. 9.2.2.4 Current Shunt Amplifier Configuration
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Pre-Production Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)

In the DRV8000-Q1, there are two VPVDD_OV thresholds, a low and high threshold. The overvoltage response options are dependent on the driver outputs configured (High-side, EC, Heater driver, Gate driver, Half-bridge drivers). There are two fault status bits available PVDD_OV_22V and PVDD_OV_28V in IC_STAT1.

The PVDD overvoltage monitor can respond and recover in two different modes set through the PVDD_OV_MODE register setting.

  • Latched Fault Mode (0b): After detecting the overvoltage condition, all drivers are disabled and FAULT register bit, and PVDD_OV_22V or PVDD_OV_28V register bit are asserted. After the overvoltage condition is removed, the fault state remains latched until CLR_FLT is issued.
  • Automatic Recovery Mode (1b): After detecting the overvoltage condition, all drivers are disabled and FAULT register bit, and PVDD_OV_22V or PVDD_OV_28V register bit asserted. After the overvoltage condition is removed, the FAULT register bit is automatically cleared and the driver automatically reenabled. The PVDD_OV_22V or PVDD_OV_28V register bit remains latched until CLR_FLT is issued.

High-side, EC and heater drivers overvoltage fault (PVDD_OV_22V):

  • High-side, EC and heater drivers shutoff when VPVDD > low VPVDD threshold voltage (22V).
  • PVDD_OV_22V fault status is defined in High-side, EC and heater drivers PVDD Overvoltage Behavior table.
  • No PVDD_OV_LVL setting available for High-side, EC and heater drivers outputs
  • PVDD_OV_MODE can be set to fault response Latched Fault or Automatic Recovery modes.

Table 7-45 High-side, EC and Heater Drivers PVDD Overvoltage Behavior
PVDD Voltage High-side, EC and Heater Drivers PVDD_OV_22V Status PVDD_OV_28V FAULT
VPVDD < 22 V Normal Operation 0b Not Applicable 0b
VPVDD > 22 V Shutdown 1b Not Applicable 1b

Half-bridges and gate driver overvoltage fault (PVDD_OV_22V or PVDD_OV_28V):

  • Half-bridges and Gate drivers support warning or shutoff when VPVDD > low VPVDD threshold voltage (22V) or shutoff for high VPVDD threshold voltage (28V).
  • PVDD_OV_22V has a configurable warning or fault condition using register PVDD_OV_LVL setting available for these driver outputs as defined in Half-bridges and Gate driver PVDD Overvoltage Behavior table.
  • The deglitch time for PVDD_OV_22V can be adjusted through the PVDD_OV_DG register settings.
  • PVDD_OV_MODE can be set to fault response Latched Fault or Automatic Recovery modes.
Table 7-46 Half-Bridges and Gate Driver PVDD Overvoltage Behavior
PVDD_OV_LVL PVDD Voltage Half-Bridges and Gate Drivers High-Side, EC and Heater Drivers PVDD_OV_22V PVDD_OV_28V FAULT
0b VPVDD < 22 V Normal Operation Normal Operation 0b 0b 0b
0b VPVDD > 22 V Shutdown Shutdown 1b 0b 1b
1b VPVDD < 22 V Normal Operation Normal Operation 0b 0b 0b
1b 28 V> VPVDD > 22 V Normal Operation with Warning Shutdown 1b 0b 1b
1b VPVDD > 28 V Shutdown Shutdown 1b 1b 1b