SLVSH22A May   2024  – September 2025 DRV8000-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUTx HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Short-circuit Protection
          3. 7.4.2.2.3 High-side Driver Overcurrent Protection
          4. 7.4.2.2.4 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.4.3 Half-bridge Register Control
        4. 7.4.4.4 Half-Bridge ITRIP Regulation
        5. 7.4.4.5 Half-bridge Protection and Diagnostics
          1. 7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.5.2 Half-bridge Open Load Detection
          3. 7.4.4.5.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short-circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IDRIVE Calculation Example
        2. 9.2.2.2 tDRIVE Calculation Example
        3. 9.2.2.3 Maximum PWM Switching Frequency
        4. 9.2.2.4 Current Shunt Amplifier Configuration
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Pre-Production Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

7.4.3.2 Electrochromic Driver Protection

The electrochromic driver block has multiple protection and detection circuits for both charge and discharge states. There are the comparator-based detection circuits, protection circuits of OUT11 which are active during EC charge state (when configured with OUT11 as supply), and protection circuits on ECFB low-side discharge MOSFET.

EC supplied by OUT11: When the electrochrome drive is configured to be supplied by integrated high-side driver OUT11, the same protection and diagnostic functions as the other high-side drivers are available (e.g. during an overcurrent detection, the control loop is switched off). These high-side driver protections are active when the electrochrome is in the charge state (voltage ramp up). When in OUT11 EC mode (OUT11_EC_MODE = 1b), OUT11 cannot be controlled in PWM mode and EC_CNFG is used to configure diagnostics. For EC_OUT11_OCP_DG when VPVDD < 20V, deglitch options (6μs, 10μs, 15μs, and 60μs) are available. For VPVDD > 20V the deglitch time is automatically reduced to 10μs.

Fault on OUT11 during EC charge: In case of an overtemperature shutdown fault (zone 3 or 4) or overcurrent fault on OUT11 while EC_ON = 1b (EC control enabled):

  • OUT11 is shut off (status register set)
  • ECDRV pin is pulled to ground
  • EC_ON remains '1'
  • ECFB_LS_EN remains as programmed

To restart EC control after OUT11 failure, the controller must read and clear the corresponding fault. The driver reverts to the previous value of EC_V_TAR when restart occurs.

If an open load is detected on OUT11 during EC charge, the OUT11_OLA bit in register HS_STAT is set.

Discharge overcurrent protection LS FET: During discharge of ECFB via low-side FET(LSFET), overcurrent fault is detected if load current on ECFB pin exceeds the overcurrent threshold (IOC_ECFB). Overcurrent fault response is configurable with EC_FLT_MODE bit in register EC_CNFG.

EC_FLT_MODE = 0b:

If the current through EC LSFET crosses the OCP threshold (IOC_ECFB) after deglitch time, LSFET is disabled. The deglitch times for the EC LSFET depend on VPVDD. For VPVDD < 20V, the deglitch time is 40μs. For VPVDD > 20V, the deglitch time is automatically reduced to 15μs.

EC_FLT_MODE = 1b:

If the current through EC LSFET after blank time crosses the OCP threshold (IOC_ECFB) for deglitch time, the driver enters overcurrent recovery mode (OCR), similar to ITRIP regulation of HS drivers OUT7-12. Deglitch time and ITRIP frequency are taken from the OUT7 ITRIP settings.

When OCR mode is enabled and if ECFB_OV bit is high due to short from ECFB to VPVDD, the driver is shutoff. The ECFB_OV deglitch time is 20μs regardless of the ECFB_OV_DG configuration settings.

Table 7-16 Discharge Overcurrent Protection
EC_FLT_MODE Fault Response
0b Latch (Hi-Z)
1b Overcurrent Recovery (OUT7 ITRIP settings)

Discharge open load detection: While discharging the EC, open-load can also be detected. Bit EC_OLEN in register EC_CNFG must be set. If the load current on ECFB is below IOL_ECFB_LS for longer than tDG_OL_ECFB_LS, then the open load status bit ECFB_OL is set, and WARN bit is set in register IC_STAT1.

Short to battery/OV detection:

ECFB overvoltage or short to battery is detected when ECFB voltage exceeds threshold VECFB_OV_TH, for longer than the deglitch time tECFB_OV_DG while EC_ON = 1. Bit ECFB_OV_MODE determines the driver ECFB overvoltage fault response. The EC overvoltage deglitch time is configured with bit ECFB_OV_DG in register EC_CNFG.

For over voltage fault response control, bit ECFB_OV_MODE can be configured in register EC_CNFG. If ECFB_OV_MODE = 00b, then no action is taken during this fault. For ECFB_OV_MODE = 01b, when ECFB voltage exceeds 3V for longer than programmed deglitch time tECFB_OV_DG, then the ECFB_OV bit is set in EC_HEAT_ITRIP_STAT register, and EC_HEAT fault bit is set in registeIC_STAT1r. For ECFB_OV_MODE = 10b, when OV on ECFB occurs, the ECDRV pin is pulled down, and the ECFB LS FET is Hi-Z. Faults are reported in the same registers as for when ECFB_OV_MODE = 01b.

The fault responses and bit values are summarized in the table below:

Table 7-17 Electrochrome Overvoltage Fault Response
ECFB_OV_MODE Fault Response
00b No action
01b Report fault in register
10b Pulldown ECDRV and ECFB LS FET, report fault in register
11b No action
Table 7-18 EC Overvoltage Deglitch Times
ECFB_OV_DG Deglitch Time
00b 20μs
01b 50μs
10b 100μs
11b 200μs

Short-circuit or open-load detection: The EC diagnostics can be configured to report either a short-circuit or an open load. This mode is selected by setting the ECFB_DIAG bits in the EC_CNFG register, with the requirement that the EC_ON bit must be 0b.

Table 7-19 ECFB Diagnostic Detection Options
ECFB_DIAG Detection Setting
00b Disabled
01b Short-circuit
10b Open Load

Short-circuit detection: The short-circuit detection can detect a low-impedance condition across ECFB to GND. The bits ECFB_SC_RSEL select the impedance under which a short-circuit is detected from 0.5Ω to 3Ω. The voltage VECFB_SC_TH is compared to IECFB_SC * ECFB_SC_RSEL. The short-circuit detection below runs when the EC amplifier is off, ECFB_DIAG = 01b, and EC_ON = 0b:

  • Run IECFB_SC current into the ECFB pin and wait an initial 3ms blanking time
  • If the ECFB voltage is less than IECFB_SC * ECFB_SC_RSEL after enabling the short-circuit detection, register a short-circuit (ECFB_SC) by setting ECFB_DIAG_STAT = 1b.
  • The IECFB_SC continues to run through ECFB pin as long as short-circuit detection is active.
Table 7-20 ECFB Diagnostic Detection Options
ECFB_SC_RSEL Impedance Threshold
00b 0.5Ω
01b 1.0Ω
10b 2.0Ω
11b 3.0Ω

Open-load detection: The passive open load detection is active when ECFB_DIAG = 10b, EC_ON = 0b, the EC amplifier is off. An open load is detected when the output impedance is greater than 4kΩ, resulting in an ECFB voltage threshold of IECFB_OLP * 4kΩ which is VECFB_OLP_TH. The procedure for open load detection is:

  • Run IECFB_OLP current into the ECFB pin and wait an initial 3ms blanking time
  • If the ECFB voltage detected is greater than VECFB_OLP_TH, register an open-load condition (ECFB_OLP) by setting ECFB_DIAG_STAT = 1b.
  • The IECFB_OLP continues to run through ECFB pin as long as open-load detection is active.