SLVSH22A May   2024  – September 2025 DRV8000-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUTx HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Short-circuit Protection
          3. 7.4.2.2.3 High-side Driver Overcurrent Protection
          4. 7.4.2.2.4 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.4.3 Half-bridge Register Control
        4. 7.4.4.4 Half-Bridge ITRIP Regulation
        5. 7.4.4.5 Half-bridge Protection and Diagnostics
          1. 7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.5.2 Half-bridge Open Load Detection
          3. 7.4.4.5.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short-circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IDRIVE Calculation Example
        2. 9.2.2.2 tDRIVE Calculation Example
        3. 9.2.2.3 Maximum PWM Switching Frequency
        4. 9.2.2.4 Current Shunt Amplifier Configuration
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Pre-Production Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information
7.4.2.1.3 OUTx HS ITRIP Behavior

For all high-side drivers, a fixed frequency current regulation feature called HS ITRIP is available. This function restarts the driver when an overcurrent condition occurs while driving certain loads. The overcurrent detection is based on sensed load current. This feature is intended to be used to drive loads with large inrush currents that exceed the overcurrent threshold of the driver, loads such as a lamp, bulb, or large LED module.

High side drivers can be configured to enable ITRIP regulation by setting the OUT7_ITRIP_EN in the HS_REG_CNFG1 register for OUT7 and the HS_OUTx_ITRIP_EN for OUT8-12 in HS_REG_CNFG3 register. By default, ITRIP regulation is disabled for all High-side drivers. If ITRIP regulation is disabled and after the blank time if the driver current exceeds overcurrent threshold (IOCx) for deglitch time, the output is disabled.

ITRIP regulation enabled:

When ITRIP regulation is enabled and after blank time if driver current exceeds overcurrent threshold IOCx for deglitch time, the output turns OFF. It automatically turns ON again after the end of ITRIP cycle. Overcurrent thresholds (high or low) are configured by setting OUT7_RDSON_MODE bit for OUT7 and OUTx_OC_TH bits for OUT8-12 in HS_OC_CNFG register.

Blank time for ITRIP regulation is 40μs for all high-side driver outputs. Blank time starts when OUTx is enabled. OUT7 has dedicated ITRIP frequency and deglitch time settings, configurable via bits OUT7_ITRIP_FREQ and OUT7_ITRIP_DG in the HS_REG_CNFG1 register. For OUT8-12, ITRIP frequency and deglitch time settings are shared, configurable via bits HS_OUT_ITRIP_FREQ and HS_OUT_ITRIP_DG in the HS_REG_CNFG3 register. For VPVDD < 20V, all deglitch options (24, 32, 40, and 48μs) are available. For VPVDD > 20V the deglitch time is automatically reduced to 10μs.

When ITRIP regulation is enabled and if an overcurrent detection is detected, OUT7_ITRIP_STAT bit in EC_HEAT_ITRIP_STAT register for OUT7 driver or OUTx_ITRIP_STAT bit in HS_ITRIP_STAT register for OUT8-12 drivers is set and latched. The fault bit remains set until the CLR_FLT bit is asserted.

Table 7-13 High-Side ITRIP Frequency Option Summary
Frequency (fITRIP_HS) HS_OUT_ITRIP_FREQ/OUT7_ITRIP_FREQ
1.7 kHz 00b
2.2 kHz 01b
3 kHz 10b
4.4 kHz 11b
Table 7-14 High-Side ITRIP Deglitch Option Summary
Deglitch Time (tITRIP_HS_DG) HS_OUT_ITRIP_DG/OUT7_ITRIP_DG
48 μs 00b
40 μs 01b
32 μs 10b
24 μs 11b

The ITRIP deglitch timer starts when the OUTx ITRIP blank time expires. The minimum OUTx ITRIP ON time is the sum of blanking and deglitch times, and total period is determined by the OUTx ITRIP frequency. The diagram below shows the ITRIP behavior.

DRV8000-Q1 OUTx HS ITRIP Behavior with Incandescent Bulb Figure 7-5 OUTx HS ITRIP Behavior with Incandescent Bulb

The blanking time tSC_BLK is 40μs, after which the overcurrent condition can be detected. tOUT7_ITRIP_DG or tHS_OUT_ITRIP_DG is the time OUTx remains on after overcurrent protection threshold is exceeded. TOUT7_ITRIP_FREQ or THS_OUT_ITRIP_FREQ is the time period of the ITRIP loop, inverse of tOUT7_ITRIP_FREQ or tHS_OUT_ITRIP_FREQ. ITRIP faults for OUT7-12 are reported in registers OUT7_ITRIP_STAT and OUTx_ITRIP_STAT.