SLVSH22A May   2024  – September 2025 DRV8000-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information RGZ package
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 External Components
    4. 7.4 Feature Description
      1. 7.4.1 Heater MOSFET Driver
        1. 7.4.1.1 Heater MOSFET Driver Control
        2. 7.4.1.2 Heater MOSFET Driver Protection
          1. 7.4.1.2.1 Heater SH_HS Internal Diode
          2. 7.4.1.2.2 Heater MOSFET VDS Overcurrent Protection (HEAT_VDS)
          3. 7.4.1.2.3 Heater MOSFET Open Load Detection
      2. 7.4.2 High-Side Drivers
        1. 7.4.2.1 High-side Driver Control
          1. 7.4.2.1.1 High-side Driver PWM Generator
          2. 7.4.2.1.2 Constant Current Mode
          3. 7.4.2.1.3 OUTx HS ITRIP Behavior
          4. 7.4.2.1.4 High-side Drivers - Parallel Outputs
        2. 7.4.2.2 High-side Driver Protection Circuits
          1. 7.4.2.2.1 High-side Drivers Internal Diode
          2. 7.4.2.2.2 High-side Driver Short-circuit Protection
          3. 7.4.2.2.3 High-side Driver Overcurrent Protection
          4. 7.4.2.2.4 High-side Driver Open Load Detection
      3. 7.4.3 Electrochromic Glass Driver
        1. 7.4.3.1 Electrochromic Driver Control
        2. 7.4.3.2 Electrochromic Driver Protection
      4. 7.4.4 Half-bridge Drivers
        1. 7.4.4.1 Half-bridge Control
        2. 7.4.4.2 OUT1 and OUT2 High-side Driver Mode
        3. 7.4.4.3 Half-bridge Register Control
        4. 7.4.4.4 Half-Bridge ITRIP Regulation
        5. 7.4.4.5 Half-bridge Protection and Diagnostics
          1. 7.4.4.5.1 Half-Bridge Off-State Diagnostics (OLP)
          2. 7.4.4.5.2 Half-bridge Open Load Detection
          3. 7.4.4.5.3 Half-Bridge Overcurrent Protection
      5. 7.4.5 Gate Drivers
        1. 7.4.5.1 Input PWM Modes
          1. 7.4.5.1.1 Half-Bridge Control
          2. 7.4.5.1.2 H-Bridge Control
          3. 7.4.5.1.3 DRVOFF - Gate Driver Shutoff Pin
        2. 7.4.5.2 Smart Gate Driver - Functional Block Diagram
          1. 7.4.5.2.1  Smart Gate Driver
          2. 7.4.5.2.2  Functional Block Diagram
          3. 7.4.5.2.3  Slew Rate Control (IDRIVE)
          4. 7.4.5.2.4  Gate Driver State Machine (TDRIVE)
            1. 7.4.5.2.4.1 tDRIVE Calculation Example
          5. 7.4.5.2.5  Propagation Delay Reduction (PDR)
          6. 7.4.5.2.6  PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
          7. 7.4.5.2.7  PDR Post-Charge/Post-Discharge Control Loop Operation Details
            1. 7.4.5.2.7.1 PDR Post-Charge/Post-Discharge Setup
          8. 7.4.5.2.8  Detecting Drive and Freewheel MOSFET
          9. 7.4.5.2.9  Automatic Duty Cycle Compensation (DCC)
          10. 7.4.5.2.10 Closed Loop Slew Time Control (STC)
            1. 7.4.5.2.10.1 STC Control Loop Setup
        3. 7.4.5.3 Tripler (Double-Stage) Charge Pump
        4. 7.4.5.4 Wide Common Mode Differential Current Shunt Amplifier
        5. 7.4.5.5 Gate Driver Protection Circuits
          1. 7.4.5.5.1 MOSFET VDS Overcurrent Protection (VDS_OCP)
          2. 7.4.5.5.2 Gate Driver Fault (VGS_GDF)
          3. 7.4.5.5.3 Offline Short-circuit and Open Load Detection (OOL and OSC)
      6. 7.4.6 Sense Output (IPROPI)
      7. 7.4.7 Protection Circuits
        1. 7.4.7.1 Fault Reset (CLR_FLT)
        2. 7.4.7.2 DVDD Logic Supply Power on Reset (DVDD_POR)
        3. 7.4.7.3 PVDD Supply Undervoltage Monitor (PVDD_UV)
        4. 7.4.7.4 PVDD Supply Overvoltage Monitor (PVDD_OV)
        5. 7.4.7.5 VCP Charge Pump Undervoltage Lockout (VCP_UV)
        6. 7.4.7.6 Thermal Clusters
        7. 7.4.7.7 Watchdog Timer
        8. 7.4.7.8 Fault Detection and Response Summary Table
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
      2. 7.5.2 SPI Format
      3. 7.5.3 Timing Diagrams
  9. 8  DRV8000-Q1 Register Map
    1. 8.1 DRV8000-Q1_STATUS Registers
    2. 8.2 DRV8000-Q1_CNFG Registers
    3. 8.3 DRV8000-Q1_CTRL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IDRIVE Calculation Example
        2. 9.2.2.2 tDRIVE Calculation Example
        3. 9.2.2.3 Maximum PWM Switching Frequency
        4. 9.2.2.4 Current Shunt Amplifier Configuration
    3. 9.3 Initialization Setup
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Bulk Capacitance Sizing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Pre-Production Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Power supply pin voltage PVDD –0.3 40 V
Power supply transient voltage ramp PVDD 2 V/µs
Digital Logic power supply voltage ramp DVDD 2 V/µs
Voltage difference between ground pins GND, PGND –0.3 0.3 V
Charge pump pin voltage VCP –0.3 PVDD + 15 V
Charge pump high-side pin voltage CP1H VPVDD – 0.3 VVCP + 0.3 V
Charge pump high-side pin voltage CP2H VPVDD – 0.6 VVCP + 0.3 V
Charge pump low-side pin voltage CP1L, CP2L –0.3 VPVDD + 0.3 V
Digital regulator pin voltage DVDD –0.3 5.75 V
Logic pin voltage GD_INx, PWM1, IPROPI/PWM2, DRVOFF, nSLEEP, SCLK, SDI, nSCS –0.3 5.75 V
Output logic pin voltage SDO –0.3 VDVDD + 0.3 V
Output pin voltage OUT1-OUT12 –0.3 VPVDD + 0.9 V
Output current OUT1-OUT12, ECFB, ECDRV Internally Limited Internally Limited A
Heater and Electrochromic MOSFET gate drive pin voltage GH_HS VSH_HS – 0.3 to VSH_HS + 13 VVCP + 0.3 V
Heater and Electrochromic MOSFET source pin voltage SH_HS, ECFB, ECDRV –0.3 VPVDD + 0.3 V
High-side driver and Heater MOSFET source pin maximum energy dissipation, TJ = 25°C, LLOAD < 100 µH OUT7-OUT12, SH_HS - 1 mJ
High-side gate drive pin voltage GHx (2) –2 VVCP + 0.3 V
Transient 1-µs high-side gate drive pin voltage GHx (2) –5 VVCP + 0.3 V
High-side gate drive pin voltage with respect to SHx GHx (2) –0.3 13.5 V
High-side sense pin voltage SHx (2) –2 40 V
Transient 1-µs high-side sense pin voltage SHx (2) –5 40 V
Low-side gate drive pin voltage GLx (2) –2 13.5 V
Transient 1-µs low-side gate drive pin voltage GLx (2) –3 13.5 V
Low-side gate drive pin voltage with respect to SL GLx (2) –0.3 13.5 V
Low-side sense pin voltage SL (2) –2 2 V
Transient 1-µs low-side sense pin voltage SL (2) –3 3 V
Gate drive current GHx, GLx Internally Limited Internally Limited A
Amplifier input pin voltage SN, SP –2 VVCP + 0.3 V
Transient 1-µs amplifier input pin voltage SN, SP –5 VVCP + 0.3 V
Amplifier input differential voltage SN, SP –5.75 5.75 V
Amplifier output pin voltage SO –0.3 VDVDD + 0.3 V
Ambient temperature, TA –40 125 °C
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) PVDD with respect to GHx, SHx, GLx, or SL should not exceed 40 V. When PVDD is greater than 35 V, negative voltage on GHx, SHx GLx, and SL should be limited to ensure this rating is not exceeded. When PVDD is less than 35 V, the full negative rating of GHx, SHx, GLx, and SL is available.