SPRACM3E August   2021  – January 2023 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DK-Q1

 

  1.   Using the Fast Serial Interface (FSI) With Multiple Devices in an Application
  2.   Trademarks
  3. 1Introduction to the FSI Module
  4. 2FSI Applications
  5. 3Handshake Mechanism
    1. 3.1 Daisy-Chain Handshake Mechanism
    2. 3.2 Star Handshake Mechanism
  6. 4Sending and Receiving FSI Data Frames
    1. 4.1 FSI Data Frame Configuration APIs
    2. 4.2 Start Transmitting Data Frames
  7. 5Daisy-Chain Topology Tests
    1. 5.1 Two Device FSI Communication
      1. 5.1.1 CPU Control
      2. 5.1.2 DMA Control
      3. 5.1.3 Hardware Control
    2. 5.2 Three Device FSI Communication
      1. 5.2.1 CPU/DMA Control
      2. 5.2.2 Hardware Control
        1. 5.2.2.1 Skew Compensation for Three Device Daisy-Chain System
          1. 5.2.2.1.1 CPU/DMA control
          2. 5.2.2.1.2 Hardware Control
  8. 6Star Topology Tests
  9. 7Event Synchronization Over FSI
    1. 7.1 Introduction
      1. 7.1.1 Requirement of Event Sync for Distributed Systems
      2. 7.1.2 Solution Using FSI Event Sync Mechanism
      3. 7.1.3 Functional Overview of FSI Event Sync Mechanism
    2. 7.2 C2000Ware FSI EPWM Sync Examples
      1. 7.2.1 Location of the C2000Ware Example Project
      2. 7.2.2 Summary of Software Configurations
        1. 7.2.2.1 Lead Device Configuration
        2. 7.2.2.2 Node Device Configuration
      3. 7.2.3 1 Lead and 2 Node F28002x Device Daisy-Chain Tests
        1. 7.2.3.1 Hardware Setup and Configurations
        2. 7.2.3.2 Experimental Results
      4. 7.2.4 1 Lead and 8 Node F28002x Device Daisy-Chain Tests
        1. 7.2.4.1 Hardware Setup and Configurations
        2. 7.2.4.2 Experimental Results
      5. 7.2.5 Theoretical C2000 Uncertainties
    3. 7.3 Additional Tips and Usage of FSI Event Sync
      1. 7.3.1 Running the Example
      2. 7.3.2 Target Configuration File
      3. 7.3.3 Usage of Event Sync for Star Configuration
  10. 8References
  11. 9Revision History

5.1.1 CPU Control

  • Test condition

    Device 1 sends data -> Device 2 receives data -> Device 2 CPU moves RX data to TX buffer and registers -> Device 2 triggers FSI TX with SW which forwards the received data back to Device 1 -> Device1 receives data back and the CPU verifies it matches the originally sent TX data.

  • Test case

    Data length of 8 words, two data lines, TXCLK = 50 MHz, with Setting ① (Table 5-1) enabled.

In the test, general-purpose input/output (GPIO)s are toggled within software when specific events occur during the communication and measured using an oscilloscope to obtain the respective timing data. In Figure 5-3, the green signal represents the GPIO toggling of Device 1 (Lead device) and the magenta signal represents the GPIO toggling of Device 2 (Node device).

GUID-FAD8B751-A7D2-4C3C-A33B-908B2D0F973E-low.png Figure 5-3 Data Transmission Test Using CPU Control

From the results shown in Figure 5-3, the time obtained for the data transmission is ~1.4 µs. In order to calculate the transmission speed, the total data length should be considered. Table 5-2 shows the general structure of a data frame, which can be divided into two parts: effective data bits and overhead bits.

  • Effective Data Bits: Includes the 8-bit User Data, 16-bit Data Words, and 8-bit CRC fields
  • Overhead Bits: Includes the Preamble, SOF, Frame Type, EOF, and Postamble fields

Therefore, the ideal transmission time for 8 words can be derived theoretically, as shown in Table 5-3.

It should be noted that since two data lines only work for effective data bits, one FSITXCLK cycle delivers 4 effective data bits, while one FSITXCLK cycle only delivers 2 overhead bits. Thus, with a total 48 FSITXCLK cycles for 8 data words, the transmission time can be calculated as shown in Equation 1.

Equation 1. (FSITXCLK cycles)/(FSITXCLK frequency) = 48/50MHz=0.96 μs

Therefore, the theoretical transmission speed is 175 Mbps (168/0.96 µs), while the speed from the test is 120 Mbps with 1.4 µs transmission time, due to the fact that the tested transmission time includes entering the ISR (to toggle an IO pin), delay introduced by isolators, transceivers, cables, and so forth. If changing to one data line, the theoretical transmission speed is 100 Mbps, while the test speed is 80 Mbps with a transmission time of 2.1 µs.

Another finding from Figure 5-3 is that moving data from the FSIRX buffers to the FSITX buffers in the node device takes some time, approximately 4.9 µs using the FSI driverLib functions. This will be a key factor that distinguishes DMA and HW controls as shown in the next sections.

Note: The time to move data between the FSI buffers and registers can be optimized by writing to and reading from the FSI registers directly instead of using the provided driverLib functions.
Table 5-2 Data Frame Structure
IDLE Preamble SOF Frame Type User Data Data Words CRC Frame Tag EOF Postamble IDLE
1111 1001 0011 8 bits N words 8 bits 4 bits 0110 1111
Table 5-3 Calculated Transmission Time for 8 Words
Effective Data Bits (bits) Overhead Bits (bits) Total Length (bits) FSITXCLK Cycles for Effective Data Bits (cycles) FSITXCLK Cycles for Overhead Bits (cycles) Total Data Transmission Time (us)
144 24 168 36 12 0.96