SPRACV0A February   2021  – March 2023 TMS320F2800132 , TMS320F2800132 , TMS320F2800133 , TMS320F2800133 , TMS320F2800135 , TMS320F2800135 , TMS320F2800137 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280023C , TMS320F280025 , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280033 , TMS320F280034 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C , TMS320F280049C-Q1 , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28076 , TMS320F28374D , TMS320F28374D , TMS320F28374S , TMS320F28374S , TMS320F28375D , TMS320F28375D , TMS320F28375S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376D , TMS320F28376S , TMS320F28376S , TMS320F28377D , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378D , TMS320F28378S , TMS320F28378S , TMS320F28379D , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28379S , TMS320F28384D , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388D , TMS320F28388S , TMS320F28388S , TMS320F28P550SJ , TMS320F28P550SJ , TMS320F28P559SJ-Q1 , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P650SK , TMS320F28P659DK-Q1 , TMS320F28P659DK-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Resources
      1. 1.1.1 TINA-TI SPICE-Based Analog Simulation Program
      2. 1.1.2 PSPICE for TI Design and Simulation Tool
      3. 1.1.3 Application Report: ADC Input Circuit Evaluation for C2000 MCUs
      4. 1.1.4 TI Precision Labs - SAR ADC Input Driver Design Series
      5. 1.1.5 Analog Engineer's Calculator
      6. 1.1.6 TI Precision Labs - Op Amps: Stability Series
        1. 1.1.6.1 Related Application Reports
      7. 1.1.7 TINA-TI ADC Input Models
  4. 2Charge-Sharing Concept
    1. 2.1 Traditional High-Speed ADC Driving Circuits
    2. 2.2 Increased Cs in High-Speed ADC Driving Circuits
    3. 2.3 Very Large Cs in ADC Driving Circuits
    4. 2.4 Charge-Sharing Operation
    5. 2.5 Sample Rate and Source Impedance vs. Tracking Error
    6. 2.6 Analytical Solution to Tracking Error
    7. 2.7 Charge-Sharing in Multiplexed ADCs
    8. 2.8 Charge-Sharing Circuit Advantages
    9. 2.9 Charge-Sharing Circuit Disadvantages
  5. 3Charge Sharing Design Flow
    1. 3.1 Gather Required Information
    2. 3.2 Size Cs
    3. 3.3 Verify Sample Rate, Source Impedance, and Bandwidth
    4. 3.4 Simulate Circuit Settling Performance
    5. 3.5 Input Design Worksheet
  6. 4Charge-Sharing Circuit Simulation Methods
    1. 4.1 Simulation Components
      1. 4.1.1 Vin
      2. 4.1.2 Voa , Voa_SS, and Verror
      3. 4.1.3 Rs, Cs, and Vcont
      4. 4.1.4 Ch, Ron, and Cp
      5. 4.1.5 S+H Switch, Discharge Switch, tacq, and tdis
    2. 4.2 Configure the Simulation Parameters
    3. 4.3 Simulating Op-amp Steady-State Voltage
    4. 4.4 Measure the Settling Error
    5. 4.5 Sweeping Source Resistance
  7. 5Example Circuit Designs
    1. 5.1 Example 1: Determining Maximum Sample Rate
      1. 5.1.1 Example 1: Analysis
      2. 5.1.2 Example 1: Simulation
      3. 5.1.3 Example 1: Worksheet
    2. 5.2 Example 2: Adding an Op-amp
      1. 5.2.1 Example 2: Analysis
      2. 5.2.2 Example 2: Simulation
      3. 5.2.3 Example 2: Worksheet
    3. 5.3 Example 3: Reduced Settling Target
      1. 5.3.1 Example 3: Analysis
      2. 5.3.2 Example 3: Simulation
      3. 5.3.3 Example 3: Worksheet
    4. 5.4 Example 4: Voltage Divider
      1. 5.4.1 Example 4: Analysis
      2. 5.4.2 Example 4: Simulation
      3. 5.4.3 Example 4: Worksheet
  8. 6Summary
  9.   A Appendix: ADC Input Settling Motivation
    1.     A.1 Mechanism of ADC Input Settling
    2.     A.2 Symptoms of Inadequate Settling
      1.      A.2.1 Distortion
      2.      A.2.2 Memory Cross-Talk
      3.      A.2.3 Accuracy
      4.      A.2.4 C2000 ADC Architecture
  10.   References
  11.   Revision History

2.4 Charge-Sharing Operation

Figure 2-2 demonstrates a typical charge-sharing input circuit design as well as the conceptual settling operation sample-to-sample. Cs is set to a very large value. Specifically in this case, Cs is set to 100nF, which is roughly 2(12+1) times as large as the internal ADC S+H capacitor, CH. This will ensure that the drop in charge on Cs when sampling is only 0.5 LSBs at 12-bit ADC resolution.

The right sub-plot of Figure 2-2 shows the conceptual settling operation for this charge-sharing input design. At the beginning of each sample, the charge between Cs and CH quickly equalizes, causing Cs to drop less than 0.5 LSBs and CH to charge to within 0.5 LSBs of the applied voltage. This ensures that CH reaches the settling target even when the S+H duration is very short. In the time between samples CH is recharged from the source voltage through Rs. This example assumes the ADC is sampling slow enough that Cs can be almost completely recharge between samples. The next section will explore how feasible this assumption is.

GUID-0CA79721-77BC-4FF3-89DE-6452B66B906F-low.gif Figure 2-2 Charge-Sharing ADC Driving Circuit
Note: Figure 2-2 shows a 500Ω source resistance, Rs. While high speed op-amp based signal conditioning circuits usually determine and place this value intentionally, charge sharing designs are many times used to work around an existing source impedance without resorting to adding an additional op-amp to the design. This source resistance could be the output impedance of a sensor or the equivalent resistance of a voltage divider used to sense a high voltage bus. If the Rs is intentionally placed in a charge-sharing input circuit design, it is usually done so to form a low-pass filter with Cs..