SPRT759 October   2023 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Overview of IEC 60730 and UL 1998 Classifications
    1. 2.1 C2000 Capability by Device Family
  6. 3C2000 Safety Collateral
    1. 3.1 Getting Started
    2. 3.2 Functional Safety Manuals
    3. 3.3 Software Collateral
  7. 4Implementing Acceptable Measures on C2000 Real-Time MCUs
    1. 4.1 Implementation Steps
    2. 4.2 Example Mapping
    3. 4.3 Additional Best Practices
  8. 5Mapping Acceptable Control Measures to C2000 Unique Identifiers
    1. 5.1 Unique Identifier Reference
    2. 5.2 CPU Related Faults
    3. 5.3 Interrupt Related Faults
    4. 5.4 Clock Related Faults
    5. 5.5 Memory Related Faults
    6. 5.6 Internal Data Path Faults
    7. 5.7 Input/Output Related Faults
    8. 5.8 Communication, Monitoring Devices, and Custom Chip Faults
  9. 6Glossary
  10. 7References

5.1 Unique Identifier Reference

Table 5-2 is a summary of Unique IDs referenced in this section. For further details, see the device-specific Functional Safety Manual.

Note:
  • IDs in Table 5-2 may not apply to every C2000 device family. To determine if an ID applies to your device, see the mapping tables and functional safety manual.
  • If the mapping tables reference an ID not listed here it was an oversight. For more information, see the device-specific Functional Safety Manual.
Table 5-2 Summary of Referenced C2000 Unique IDs
Unique ID Short Description Notes / Software Support
ADC2 DAC to ADC loopback check
ADC8 ADC input signal integrity check
ADC10 Hardware redundancy
CAN3 SRAM Parity
CLA1 Software reciprocal comparison
CLA2 Software test of CPU CLA_STL
CLA3 Handling of illegal operation and illegal results
CLK2 Integrity using CPU timer SDL module: STL_OSC_CT
CLK3 Integrity using HRPWM SDL module: STL_OSC_HR
CLK4 Dual clock comparator (DCC type0)
CLK16 Dual clock comparator (DCC type1) Note: DCC type 1 is identical to type 2.
CLK17 Dual clock comparator (DCC type2)
CPU1 Software reciprocal comparison
CPU2 Hardware built-in test of CPU SDL module: STL_HWBIST
CPU3 Software test of CPU C28X_STL
CPU7 Handling of illegal operation, illegal results and instruction trapping
DCSM2 Majority voting and error detection of link pointer
ECAT6 SRAM parity
EFUSE2 EFUSE ECC (data only)
FLASH1 Flash ECC (data + address)
FLASH2 VCU CRC check of memory SDL module: STL_CRC
FLASH6 Software test of ECC logic SDL modules: sdl_ex_ram_ecc_parity_test and sdl_ex_flash_ecc_test
GPIO4 Software test of function using I/O loopback
GPIO5 Hardware redundancy
INC1 Software test of function including error tests
INC8 Transmission redundancy
INC9 Hardware redundancy
MCAN8 SRAM ECC (data + address)
PIE1 PIE double SDRAM hardware comparison
PIE2 Software test of SRAM
PIE3 Software test of ePIE including error tests
PIE6 PIE double SRAM comparison check SDL module: STL_PIE_RAM
PIE8 Online monitoring of interrupts and events
PIE13 Hardware redundancy using lockstep compare
ROM1 VCU CRC check of memory SDL module: STL_CRC
ROM9 Background CRC for CLA program ROM
ROM10 Memory power-on Self-test (MPOST)
ROM15 ROM parity
SRAM1 SRAM ECC (data + address)
SRAM2 SRAM Parity
SRAM3 Software test of SRAM SDL module: STL_March
SRAM8 VCU CRC check of memory SDL module: STL_CRC
SRAM14 Software test of parity logic SDL modules: sdl_ex_ram_ecc_parity_test
STL_CPU_REG CPU register test example from the diagnostic library For a device that does not include HWBIST, a periodic test of the CPU registers can be performed. STL_CPU_REG does not map to a C2000 Unique ID directly. STL_CPU_REG refers to an example CPU register test within the diagnostic library. This example is also provided for other devices if needed. Refer to the diagnostic library documentation.