SPRUIF3B May 2017 – March 2019 DRA790 , DRA791 , DRA793 , DRA797
The SoC supports a variety of different boot modes, which is determined by the 16-bit system boot setting present on the shared specific I/O balls during power-on sequence (see the TRM for details). Boot mode selection is accomplished by the setting of DIP switches SW3 and SW4, as shown in Table 6, before cycling power.
These SoC resources can be redeployed through both SoC pin EVM MUX settings to support alternate interfaces after boot-up.
SoC Interface
(Internal System Boot Input) |
CPU Board Net | DIP Switch Reference Designator Position
Number Connections |
Factory Setting |
---|---|---|---|
GPMC_AD0
(sysboot0) |
GPMC_D00 | SW3.P1 | On |
GPMC_AD1
(sysboot1) |
GPMC_D01 | SW3.P2 | Off |
GPMC_AD2
(sysboot2) |
GPMC_D02 | SW3.P3 | On |
GPMC_AD3
(sysboot3) |
GPMC_D03 | SW3.P4 | Off |
GPMC_AD4
(sysboot4) |
GPMC_D04 | SW3.P5 | On |
GPMC_AD5
(sysboot5) |
GPMC_D05 | SW3.P6 | Off |
GPMC_AD6
(sysboot6) |
GPMC_D06 | SW3.P7 | Off |
GPMC_AD7
(sysboot7) |
GPMC_D07 | SW3.P8 | Off |
GPMC_AD8
(sysboot8) |
GPMC_D08 | SW4.P1 | On |
GPMC_AD9
(sysboot9) |
GPMC_D09 | SW4.P2 | Off |
GPMC_AD10
(sysboot10) |
GPMC_D10 | SW4.P3 | Off |
GPMC_AD11
(sysboot11) |
GPMC_D11 | SW4.P4 | Off |
GPMC_AD12
(sysboot12) |
GPMC_D12 | SW4.P5 | Off |
GPMC_AD13
(sysboot13) |
GPMC_D13 | SW4.P6 | Off |
GPMC_AD14
(sysboot14) |
GPMC_D14 | SW4.P7 | Off |
GPMC_AD15
(sysboot15) |
GPMC_D15 | SW4.P8 | On |
In addition to SoC boot settings, EVM resources must also be set for the desired boot interface. Table 7 lists the boot interfaces that require selection. DIP switch SW8 is used to configure the various boot memories.
Signals | Description | DIP Switch | Factory Setting |
---|---|---|---|
NAND_BOOTn(1) | On: Enable GPMC_nCS0 for NAND flash boot | SW8.1 | Off |
NOR_BOOTn(1) | On: Enable GPMC_nCS0 for NOR flash boot | SW8.2 | Off |
MMC2_BOOT | On: Enable MMC2 Interface for eMMC flash boot | SW8.3 | Off |
Not Used | Not Used | SW8.4 | Off |
SW_VPP_EN | On: Enable VPP supply to SOC
(also requires I/O expander bit to be set) |
SW8.5 | Off |
MCASP1_ENn | Low: Enable COMx signal paths | SW8.6 | Off |
NOR_ALT_ADDRn | Off: Selects default pin location for GPMC ADDR
On: Selects alternate/new pin locations for GPMC |
SW8.7 | Off |
PCI_RESET_SEL | High: PCIe device may reset SoC.
Low: SoC may reset the PCIe device. |
SW8.8 | Off |
GPMC_WPN | Low: Enable write protection of NAND flash | SW5.9 | Off |
I2C_EEPROM_WP | High: Enable write protection of board identification EEPROM | SW5.10 | Off |