SPRUIF3B May 2017 – March 2019 DRA790 , DRA791 , DRA793 , DRA797
Dual Gigabit Ethernet ports are supported on the EVM. RGMII ports 0 and 1 drive the TI DP83867 Gigabit PHYs. The PHYs are configured through the management data input/output bus (MDIO), with address set to 0x2 (port 0) and 0x3 (port 1). PHYs are reset at power on, but can also be independently reset using the I/O expander. Both ports share a common interrupt signal (GPIO6_16).
NOTE
For PHY configuration, users must configure the RGMII Control register (RGMIICTL) of the DP83867 for RGMII mode, and configure the RGMII Delay Control register (RGMIIDCTL) for a 0-ns TX delay and 2.25-ns RX delay. Set the I/O Drive Strength register (IO_IMPEDANCE_CTRL) to maximum drive.