SPRUIF3B May   2017  – March 2019 DRA790 , DRA791 , DRA793 , DRA797

 

  1.   DRA79x EVM CPU board
    1.     Trademarks
    2. 1 Introduction
    3. 2 Overview
      1. 2.1 EVM System Configurations
      2. 2.2 CPU Board Feature List
      3. 2.3 CPU Board Component Identification
    4. 3 Hardware
      1. 3.1 Hardware Architecture
      2. 3.2 DRA71x, DRA79x, TDA2E-17, and AM570x Processor
      3. 3.3 Power Architecture
      4. 3.4 Reset Structure
      5. 3.5 Clocks
      6. 3.6 Memory
        1. 3.6.1  SDRAM Memory
        2. 3.6.2  QSPI Flash Memory
        3. 3.6.3  EMMC Flash Memory
        4. 3.6.4  MicroSD Card Cage
        5. 3.6.5  GPMC NOR Flash Memory
        6. 3.6.6  GPMC NAND Flash Memory
        7. 3.6.7  Boot Modes
        8. 3.6.8  JTAG/Emulator and Trace
        9. 3.6.9  UART Terminal
        10. 3.6.10 DCAN and CAN Interfaces
        11. 3.6.11 Universal Serial Bus (USB)
        12. 3.6.12 Wired Ethernet
        13. 3.6.13 Video Output
          1. 3.6.13.1 HDMI Display
          2. 3.6.13.2 LCD Touch Panel
          3. 3.6.13.3 FPD-Link III Output/Panel
        14. 3.6.14 Video Input
          1. 3.6.14.1 Parallel Imaging
          2. 3.6.14.2 Serial Imaging
        15. 3.6.15 Mini-PCIe
        16. 3.6.16 Media Local Bus (MLB)
        17. 3.6.17 Audio
        18. 3.6.18 COM8 Module Interface
        19. 3.6.19 eFuse Programming Supply
        20. 3.6.20 User Interface LEDs
        21. 3.6.21 Power Monitoring
        22. 3.6.22 I2C Peripheral Map
        23. 3.6.23 GPIO List
        24. 3.6.24 I/O Expander List
        25. 3.6.25 Configuration EEPROM
    5. 4 Signal Multiplex Logic
      1. 4.1 GPMC and QSPI Selection (MUX A)
      2. 4.2 GPMC, VIN1, and VOUT3 Selection (MUX B)
      3. 4.3 GPMC and EMMC Selection (MUX C)
      4. 4.4 VIN2A and EMU Selection (MUX D, MUX E)
      5. 4.5 VIN2A and RGMII1 Selection (MUX F)
      6. 4.6 RGMII0 and VIN1B Selection (MUX J)
      7. 4.7 SPI2 and UART3 Selection (MUX K)
      8. 4.8 DCAN2 and I2C3 Selection (MUX L)
    6. 5 USB3 Supported Configurations
      1. 5.1 Option 1
      2. 5.2 Option 2
      3. 5.3 Option 3
    7. 6 References
  2.   Revision History

3.6.21 Power Monitoring

The CPU board has provisions to monitor power for many of the systems core power rails. The measurement system is implemented using the INA226 I2C current shunt and power monitors from TI. The INA226 device monitors both power supply voltage and shunt current measurements. Information is connected from the INA226 devices using dedicated I2C buses. The INA226 devices can be controlled using off-board modules (FTDI USART, MSP430, or a similar device).

Table 9 lists a mapping of the current monitoring system. INA226 devices are at each shunt location.

Table 9. Power Monitor Mapping

I2C Address Power Net Shunt/Resistor Description
I2C BUS A
0x40 VPIN_S1_3V3 20 mΩ LP8733 Buck0 power input (core)
0x41 VPIN_S2_3V3 20 mΩ LP8733 Buck1 power input (DSP)
0x42 VPIN_S3_3V3 20 mΩ LP8732 Buck0 power input (1V8)
0x43 VPIN_S4_3V3 20 mΩ LP8732 Buck1 power input (DDR)
0x44 VDD_CORE_AVS 10 mΩ CPU Core power rail
0x45 VDD_DSP_AVS 10 mΩ CPU DSP power rail
0x46 VDDS_1V8 10 mΩ CPU 1V8 power rails
0x47 VDD_DDR_1V35 10 mΩ CPU DDR power rail
0x48 VDA_1V8_PLL 10 mΩ CPU PLL power rails
0x49 VDA_1V8_PHY 10 mΩ CPU PHY power rails
0x4A VDDSHV8 10 mΩ CPU I/O power rail for VDDSHV8
0x4B VDDA_USB3V3 10 mΩ CPU USB3V3 power rail
0x4C VDDSHV_3V3 10 mΩ CPU I/O power rail (except VDDSHV8)
I2C BUS B
0x40 EVM_12V 10 mΩ Total system 12-V power rail
0x41 EVM_5V0 10 mΩ Total system 5V0 power rail
0x42 VSYS_3V3 10 mΩ Total system 3V3 power rail
0x43 VDD_DDR 10 mΩ DDR memory power rail
0x44 EVM_1V8 10 mΩ EVM 1V8 peripheral rail
0x45 EVM_3V3 10 mΩ EVM 3V3 peripheral rail