SPRUJE8C December   2024  – June 2025 AM2752-Q1 , AM2754-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Preface Read This First
      1. 1.2.1 Important Usage Notes
    3. 1.3 Kit Contents
    4. 1.4 Device Information
      1. 1.4.1 Security
    5. 1.5 Audio Expansion Connectors
  6. 2Hardware
    1. 2.1  Component Identification
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Status LEDs
      3. 2.2.3 Power Tree
      4. 2.2.4 Power Sequence
      5. 2.2.5 PMIC
    3. 2.3  Reset
    4. 2.4  Clock
    5. 2.5  Boot Mode Selection
    6. 2.6  Header Information
    7. 2.7  Push Buttons
    8. 2.8  Switches
    9. 2.9  GPIO Mapping
    10. 2.10 Interfaces
      1. 2.10.1  Memory Interface
        1. 2.10.1.1 OSPI Interface
        2. 2.10.1.2 Board ID EEPROM
        3. 2.10.1.3 MMC0 Interface
        4. 2.10.1.4 HYPERRAM
      2. 2.10.2  Ethernet Interface
        1. 2.10.2.1 Ethernet Add-on Connectors
      3. 2.10.3  Audio Interfaces
        1. 2.10.3.1 Audio Clocking
        2. 2.10.3.2 McASP
        3. 2.10.3.3 MLB
      4. 2.10.4  I2C Interface
      5. 2.10.5  SPI
      6. 2.10.6  UART
      7. 2.10.7  MCAN
      8. 2.10.8  JTAG
      9. 2.10.9  USB
      10. 2.10.10 ADC
    11. 2.11 AEC Mapping
      1. 2.11.1 Audio Expansion Connector 1
      2. 2.11.2 Audio Expansion Connector 2
    12. 2.12 Test Points
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 If You need Assistance
    2. 4.2 Trademarks
    3. 4.3 Rev. E2 Design Changes
  9. 5References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used This Design
  10. 6Revision History

2.5 Boot Mode Selection

The bootmode for the AM275x is selected by two DIP switches SW2(0:7) and SW1(8:15).

AM2754, AM2754-Q1, AM2752, AM2752-Q1 Boot Mode Switches SW2 and SW1 (MMC SD Card Boot) Figure 2-15 Boot Mode Switches SW2 and SW1 (MMC SD Card Boot)
AM2754, AM2754-Q1, AM2752, AM2752-Q1 Boot Mode Switches SW2 and SW1 (UART Boot) Figure 2-16 Boot Mode Switches SW2 and SW1 (UART Boot)
AM2754, AM2754-Q1, AM2752, AM2752-Q1 Boot Mode Switches SW2 and SW1 (OSPI Boot) Figure 2-17 Boot Mode Switches SW2 and SW1 (OSPI Boot)
Table 2-6 PLL Reference Clock Selection BOOTMODE[2:0]
SW2.3 SW2.2 SW2.1 PLL REF CLK (MHz)
OFF OFF OFF RVSD
OFF OFF ON RSVD
OFF ON OFF 24MHz
OFF ON ON 25MHz
ON OFF OFF 26MHz
ON OFF ON RSVD
ON ON OFF RSVD
ON ON ON RSVD
Table 2-7 Primary Boot Mode Selection[6:3]
SW2.7 SW2.6 SW2.5 SW2.4 Primary Boot Mode Selected
OFF OFF OFF OFF Serial NAND
OFF OFF OFF ON OSPI
OFF OFF ON OFF QSPI
OFF OFF ON ON SPI
OFF ON OFF OFF RGMII1
OFF ON OFF ON RMII1
OFF ON ON OFF I2C0
OFF ON ON ON UART0
ON OFF OFF OFF MMC/SD Card (SW9 ON)
ON OFF OFF ON eMMC (SW9 OFF)
ON OFF ON OFF USB
ON OFF ON ON RSVD
ON ON OFF OFF RSVD
ON ON OFF ON Fast-xSPI
ON ON ON OFF xSPI
ON ON ON ON No-boot/Dev boot
Table 2-8 Primary Boot Mode Configuration[9:7]
SW1.2 SW1.1 SW2.8 Primary Boot Mode
RVSD Read Mode2 0: RSVD (Read mode is taken from Read Mode 1) Read Mode1 0 : OSPI/ 1-1-8 Mode (valid only when Read Mode 2 is 0) Serial NAND
1: SPI/ 1-1-1 Mode (Read mode is taken from Read Mode 2 and Read Mode 1 is ignored) 1 : QSPI/ 1-1-4 Mode (valid only when Read Mode 2 is 0)
RVSD RSVD Csel 0: Chip Select 0 OSPI
1: Chip Select 1
RVSD RSVD Csel 0: Chip Select 0 QSPI
1: Chip Select 1
RVSD Mode 0: SPI Mode 0 Csel 0: Chip Select 0 SPI
1: SPI Mode 3 1: Chip Select 1
0 0 Link stat 0: Phy scan used for speed/duplex setup RGMII1
1: RGMII status register used for speed/duplex setup
CLKOUT 0: 50MHz clock not generated on CLKOUT0 CLK SRC 0: External clock source 0 RMII1
1: 50MHz clock generated on CLKOUT0 1: Internal clock source
Bus reset 0: Hung bus reset attempt after 1ms RSVD Addr 0: 0x50 I2C0
1: No hung Bus reset attempted 1: 0x51
RSVD RSVD RSVD UART0
0 RSVD Fs/Raw 0: FileSystem Mode MMC/SD Card
1: Raw Mode
RSVD RSVD RSVD eMMC
Core Volt 0: 0.85V Core Voltage Mode 0: DFU(Device) Lane Swap 0: No swapping of DP/DM USB
1: 0.75V Core Voltage 1: TBD 1: DP/DM is swapped
RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD
RSVD RSVD RSVD Fast-xSPI
SFDP 0: SFDP disabled Read Cmd 0: 0x0B Read Command Mode 0: 1S-1S-1S mode @ 50MHz xSPI
1: SFDP enabled 1: 0xEE Read Command 1:8D-8D-8D mode @ 25 MHz
RSVD ARM/Thumb 0: ARM mode No/Dev 0: Development Boot No-boot/Dev boot
1: Thumb mode 1: No Boot
Table 2-9 Backup Bootmode Selection BOOTMODE[12:10]
SW1.5 SW1.4 SW1.3 Backup Boot Mode Selected
OFF OFF OFF None
OFF OFF ON USB
OFF ON OFF RSVD
OFF ON ON UART
ON OFF OFF Ethernet
ON OFF ON MMC/SD
ON ON OFF SPI
ON ON ON I2C
Table 2-10 Backup Bootmode Configuration BOOTMODE[13]
SW1.6 Backup Boot Mode Defaulted Values for Back up Boot Mode
RSVD None
Mode 0: DFU (Device) USB Core Volt bit = 0
Lane Swap bit = 0
1: TBD
RSVD RSVD
RSVD UART
IF 0: RGMII with internal Delay Ethernet Link Stat bit = 0 (If RGMII)
1: RGMII with external clock source ClkOut bit= 0 and Clksrc bit = 1 (If RMII)
0 MMC Mode bit = 0
RSVD SPI Csel bit = 0
Mode = 0
RSVD I2C Addr = 0
Bus Rest = 0