SPRUJH3 April   2025 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280023 , TMS320F280023C , TMS320F280025 , TMS320F280025C , TMS320F280034 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037C , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039C , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049C , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379S , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Configuring the Boot Mode
    1. 2.1 Standalone Boot
      1. 2.1.1 Boot Mode Select Pins (BMSP)
      2. 2.1.2 Boot Definition Table (BOOTDEF)
      3. 2.1.3 Boot ROM OTP Configuration Registers
      4. 2.1.4 CPU2 Boot Flow
    2. 2.2 Emulation Boot
  6. 3Programming the Flash
    1. 3.1 Flash API
    2. 3.2 Flash Kernels
  7. 4Bootloading Code to Flash
    1. 4.1 C2000 Hex Utility
    2. 4.2 Common Boot Modes
      1. 4.2.1 Boot to Flash
      2. 4.2.2 SCI Boot
      3. 4.2.3 CAN Boot
      4. 4.2.4 CAN-FD Boot
      5. 4.2.5 USB Boot
  8. 5FAQ
    1. 5.1 Selecting the BMSP GPIOs with a Software-based Implementation
    2. 5.2 Running a Flash Kernel from the Flash Instead of the RAM
    3. 5.3 No Symbols Defined When Debugging Boot ROM
    4. 5.4 Writing Values in the OTP Using the On-Chip Flash Tool
    5. 5.5 Writing Values in the OTP Using the Flash API Plugin
  9. 6Summary
  10. 7References

2.1.4 CPU2 Boot Flow

Note: This section is based on the F28P65x family of devices. Device specific information can be found in the Boot ROM chapter of the device-specific Technical Reference Manual (TRM).

While CPU1 can be booted in different modes based on the boot pin configuration, CPU2 must be booted by CPU1 using the Inter-Processor Communication (IPC) module [9]. The CPU1 application configures boot mode for CPU2 through the IPCBOOTMODE register and controls when CPU2 is released from reset to boot.

Regardless of the reset source, CPU2 requires the IPC flag to be set by CPU1 on every reset to confirm the contents of the IPCBOOTMODE register are valid and continue the boot process. CPU2 acknowledges and clears the flag during boot up.

At a high-level, the CPU2 boot sequence is as follows:

  1. CPU2 boots up and is either:
    1. Held in reset
    2. In Wait boot mode waiting for the IPC Flag
  2. CPU1 application configures the CPU1TOCPU2IPCBOOTMODE register
  3. CPU1 sets the CPU1TOCPU2IPCFLG0 to confirm the contents of CPU1TOCPU2IPCBOOTMODE are valid
  4. If CPU2 is held in reset, the CPU1 application releases CPU2
  5. CPU2 acknowledges and clears the IPC flag during boot up
  6. CPU2 boot ROM runs the specified boot mode in CPU1TOCPU2IPCBOOTMODE

The IPCBOOTMODE register bit-field configurations and requirements for booting CPU2 are shown in the IPCBOOTMODE Details section of the F28P65x TRM. Table 2-8 details how this register can be configured for F28P65x devices.

Similar to the CPU1 BOOTPIN-CONFIG and BOOTDEF registers, CPU1TOCPU2IPCBOOTMODE is configured as follows:

  1. The upper 8-bits contains the key indicating validity (0x5A)
  2. The lower 8-bits sets CPU2's boot mode
  3. Bits 16-19 specifies the number of words to be copied from CPU1TOCPU2MSGRAM1 to CPU2 M1RAM if “Copy from IPC Message RAM and Boot to M1RAM" boot mode is invoked
Table 2-8 CPU1TOCPU2IPCBOOTMODE Register Details
Bit Name Valid Values Description
31:24 Key 0x5A Key must be set for this register to be considered valid.
23:20 Reserved - Reserved
19:16 IPC Message RAM Copy Length 0x0 = 0 words (Boot mode not used)
0x1 = 100 words
0x2 = 200 words
...
0x9 = 900 words
0xA = 1000 words		 Sets the data length (in words) for the "Copy from IPC Message RAM and Boot to M1RAM" boot mode. This is the number of words to be copied from CPU1TOCPU2MSGRAM1 to CPU2 M1RAM.
If not using this boot mode, set value to 0x0.
15:8 Reserved - Reserved
7:0 CPU2 Boot Mode 0x00 = None/Wait Boot
0x01 = IPC Message RAM copy and boot to M1RAM
0x03 = Flash Boot Option 0 (Sector 0)
0x05 = Boot to M0RAM
0x0A = Secure Flash Boot Option 0 (Sector 0)
0x0B = Boot to User OTP
0x23 = Flash Boot Option 1 (Sector 4)
0x2A = Secure Flash Boot Option 1 (Sector 4)
0x43 = Flash Boot Option 2 (Sector 8)
0x4A = Secure Flash Boot Option 2 (Sector 8)
0x63 = Flash Boot Option 3 (Sector 13)
0x6A = Secure Flash Boot Option 3 (Sector 13)		 Sets the boot mode for CPU2