SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

19.2 SHA-MD5 Registers

SHAMD5 functional registers offset: 0x4403 5000.

Table 19-11 lists the memory-mapped registers for SHA/MD5. All register offset addresses not listed in Table 19-11 should be considered as reserved locations and the register contents should not be modified. Figure 19-4 shows an overview of Public World, Inner and Outer Digest registers, and usage for MD5, SHA-1, and SHA-224/256.

Table 19-11 SHA-MD5 Registers
OffsetAcronymRegister NameSection
0hSHAMD5_ODIGEST_AOuter Digest Register ASection 19.2.1
4hSHAMD5_ODIGEST_BOuter Digest Register BSection 19.2.2
8hSHAMD5_ODIGEST_COuter Digest Register CSection 19.2.3
ChSHAMD5_ODIGEST_DOuter Digest Register DSection 19.2.4
10hSHAMD5_ODIGEST_EOuter Digest Register ESection 19.2.5
14hSHAMD5_ODIGEST_FOuter Digest Register FSection 19.2.6
18hSHAMD5_ODIGEST_GOuter Digest Register GSection 19.2.7
1ChSHAMD5_ODIGEST_HOuter Digest Register HSection 19.2.8
20hSHAMD5_IDIGEST_AInner Digest Register ASection 19.2.9
24hSHAMD5_IDIGEST_BInner Digest Register BSection 19.2.10
28hSHAMD5_IDIGEST_CInner Digest Register CSection 19.2.11
2ChSHAMD5_IDIGEST_DInner Digest Register DSection 19.2.12
30hSHAMD5_IDIGEST_EInner Digest Register ESection 19.2.13
34hSHAMD5_IDIGEST_FInner Digest Register FSection 19.2.14
38hSHAMD5_IDIGEST_GInner Digest Register GSection 19.2.15
3ChSHAMD5_IDIGEST_HInner Digest Register HSection 19.2.16
40hSHAMD5_DIGEST_COUNTDigest CountSection 19.2.17
44hSHAMD5_MODESHA ModeSection 19.2.18
48hSHAMD5_LENGTHSHA LengthSection 19.2.19
80hSHAMD5_DATA0_INData input message 0Section 19.2.20
84hSHAMD5_DATA1_INData input message 1Section 19.2.21
88hSHAMD5_DATA2_INData input message 2Section 19.2.22
8ChSHAMD5_DATA3_INData input message 3Section 19.2.23
90hSHAMD5_DATA4_INData input message 4Section 19.2.24
94hSHAMD5_DATA5_INData input message 5Section 19.2.25
98hSHAMD5_DATA6_INData input message 6Section 19.2.26
9ChSHAMD5_DATA7_INData input message 7Section 19.2.27
A0hSHAMD5_DATA8_INData input message 8Section 19.2.28
A4hSHAMD5_DATA9_INData input message 9Section 19.2.29
A8hSHAMD5_DATA10_INData input message 10Section 19.2.30
AChSHAMD5_DATA11_INData input message 11Section 19.2.31
B0hSHAMD5_DATA12_INData input message 12Section 19.2.32
B4hSHAMD5_DATA13_INData input message 13Section 19.2.33
B8hSHAMD5_DATA14_INData input message 14Section 19.2.34
BChSHAMD5_DATA15_INData input message 15Section 19.2.35
110hSHAMD5_SYSCONFIGSystem ConfigSection 19.2.36
118hSHAMD5_IRQSTATUSIRQ StatusSection 19.2.37
11ChSHAMD5_IRQENABLEIRQ EnableSection 19.2.38
810hDTHE_SHA_IMSHA Interrupt Mask SetSection 19.2.39
814hDTHE_SHA_RISSHA Interrupt Raw Interrupt StatusSection 19.2.40
818hDTHE_SHA_MISSHA Interrupt Masked interrupt StatusSection 19.2.41
81ChDTHE_SHA_ICSHA Interrupt Clear Interrupt StatusSection 19.2.42
Overview of Public World, Inner and Outer Digest Registers, and Usage for MD5, SHA-1, and SHA-224/256Figure 19-4 Overview of Public World, Inner and Outer Digest Registers, and Usage for MD5, SHA-1, and SHA-224/256

Outer digest registers are only relevant for HMAC operations; contents are ignored for hash operations.

  • SHAMD5_ODIGEST_A
  • SHAMD5_ODIGEST_B
  • SHAMD5_ODIGEST_C
  • SHAMD5_ODIGEST_D
  • SHAMD5_ODIGEST_E
  • SHAMD5_ODIGEST_F
  • SHAMD5_ODIGEST_G
  • SHAMD5_ODIGEST_H

The outer digest for HMAC operations without key processing (HMAC key processing = 0) must be written to these registers before starting the operation by writing to SHAMD5_MODE. Only the relevant digest registers for the selected algorithm must be written, A-D for MD5, A-E for SHA-1, A-H for SHA-2 (224 and 256).

When HMAC key processing is 1, these registers must be written with the lower 256 bits of the HMAC key to be processed, in little-endian format (first byte of key string in bits [7:0]). If the HMAC key is less than 512 bits in size, it must be properly padded to the block size with zeroes on the most significant bytes. All 16 HMAC key registers must be written explicitly, as the core does not pad the HMAC key. Additionally, if the HMAC key is larger than 512 bits, the host is responsible for performing a preprocessing step to reduce it to one 512-bit block. This involves hashing the large key and padding the hash result with zeroes until it is 512 bits wide.

The computed outer digest can be read from these registers when the status register indicates that the operation is done or suspended due to a context switch request. If no HMAC key processing is performed, the value read here would be identical to the value written initially. The MD5 outer digest is available from digest registers A-D, the SHA-1 outer digest from registers A-E, and the SHA-224 and 256 outer digest from registers A-H.

The HMAC key itself cannot be read back from these registers, but it is preserved for future processing as long as the SHAMD5_ODIGEST registers are not overwritten; this allows reuse of the HMAC key (without having to redo the HMAC key processing) for subsequent data blocks without having to reload it. This is done by setting HMAC key processing to 0 and Reuse HMAC key to 1 in the SHAMD5_MODE register.

19.2.1 SHAMD5_ODIGEST_A Register (Offset = 0h) [reset = 0h]

SHAMD5_ODIGEST_A is shown in Figure 19-5 and described in Table 19-12.

Return to Summary Table.

WRITE: Outer Digest [127:96] for MD5, [159:128] for SHA-1, [255:224] for SHA-2 / HMAC Key [31:0] for HMAC key proc

READ: Outer Digest [127:96] for MD5, [159:128] for SHA-1, [255:224] for SHA-2

Figure 19-5 SHAMD5_ODIGEST_A Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-12 SHAMD5_ODIGEST_A Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.2 SHAMD5_ODIGEST_B Register (Offset = 4h) [reset = 0h]

SHAMD5_ODIGEST_B is shown in Figure 19-6 and described in Table 19-13.

Return to Summary Table.

WRITE: Outer Digest [95:64] for MD5, [127:96] for SHA-1, [223:192] for SHA-2 / HMAC Key [63:32] for HMAC key proc

READ: Outer Digest [95:64] for MD5 [127:96] for SHA-1, [223:192] for SHA-2

Figure 19-6 SHAMD5_ODIGEST_B Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-13 SHAMD5_ODIGEST_B Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.3 SHAMD5_ODIGEST_C Register (Offset = 8h) [reset = 0h]

SHAMD5_ODIGEST_C is shown in Figure 19-7 and described in Table 19-14.

Return to Summary Table.

WRITE: Outer Digest [63:32] for MD5, [95:64] for SHA-1, [191:160] for SHA-2 / HMAC Key [95:64] for HMAC key proc

READ: Outer Digest [63:32] for MD5 [95:64] for SHA-1, [191:160] for SHA-2

Figure 19-7 SHAMD5_ODIGEST_C Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-14 SHAMD5_ODIGEST_C Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.4 SHAMD5_ODIGEST_D Register (Offset = Ch) [reset = 0h]

SHAMD5_ODIGEST_D is shown in Figure 19-8 and described in Table 19-15.

Return to Summary Table.

WRITE: Outer Digest [31:0] for MD5 [63:31] for SHA-1, [159:128] for SHA-2 / HMAC Key [127:96] for HMAC key proc

READ: Outer Digest [31:0] for MD5 [63:32] for SHA-1, [159:128] for SHA-2

Figure 19-8 SHAMD5_ODIGEST_D Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-15 SHAMD5_ODIGEST_D Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.5 SHAMD5_ODIGEST_E Register (Offset = 10h) [reset = 0h]

SHAMD5_ODIGEST_E is shown in Figure 19-9 and described in Table 19-16.

Return to Summary Table.

WRITE: Outer Digest [31:0] for SHA-1, [127:96] for SHA-2 / HMAC Key [159:128] for HMAC key proc

READ: Outer Digest [31:0] for SHA-1, [127:96] for SHA-2

Figure 19-9 SHAMD5_ODIGEST_E Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-16 SHAMD5_ODIGEST_E Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.6 SHAMD5_ODIGEST_F Register (Offset = 14h) [reset = 0h]

SHAMD5_ODIGEST_F is shown in Figure 19-10 and described in Table 19-17.

Return to Summary Table.

WRITE: Outer Digest [95:64] for SHA-2 / HMAC Key [191:160] for HMAC key proc

READ: Outer Digest [95:64] for SHA-2

Figure 19-10 SHAMD5_ODIGEST_F Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-17 SHAMD5_ODIGEST_F Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.7 SHAMD5_ODIGEST_G Register (Offset = 18h) [reset = 0h]

SHAMD5_ODIGEST_G is shown in Figure 19-11 and described in Table 19-18.

Return to Summary Table.

WRITE: Outer Digest [63:32] for SHA-2 / HMAC Key [223:192] for HMAC key proc

READ: Outer Digest [63:32] for SHA-2

Figure 19-11 SHAMD5_ODIGEST_G Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-18 SHAMD5_ODIGEST_G Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.8 SHAMD5_ODIGEST_H Register (Offset = 1Ch) [reset = 0h]

SHAMD5_ODIGEST_H is shown in Figure 19-12 and described in Table 19-19.

Return to Summary Table.

WRITE: Outer Digest [31:0] for SHA-2 / HMAC Key [255:224] for HMAC key proc

READ: Outer Digest [31:0] for SHA-2

Figure 19-12 SHAMD5_ODIGEST_H Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-19 SHAMD5_ODIGEST_H Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

Inner digest registers: The following registers hold the inner digest for HMAC and hash operations:

  • SHAMD5_IDIGEST_A
  • SHAMD5_IDIGEST_B
  • SHAMD5_IDIGEST_C
  • SHAMD5_IDIGEST_D
  • SHAMD5_IDIGEST_E
  • SHAMD5_IDIGEST_F
  • SHAMD5_IDIGEST_G
  • SHAMD5_IDIGEST_H

The inner or initial digest for HMAC and hash continue (HMAC key processing = 0 and use algorithm constants = 0) operations must be written to these registers before starting the operation by writing to S_HASH_MODE. Only the relevant digest registers for the selected algorithm must be written, A-D for MD5, A-E for SHA-1, A-H for SHA-2. When use algorithm constants is 1, these registers do need not to be written, because they are overwritten with the appropriate algorithm constants.

For HMAC operations with key preprocessing enabled (HMAC key processing = 1), these registers must be written with the upper 256 bits of the HMAC key, in little-endian format (first byte of key string in bits [7:0]). If the HMAC key is less than 512 bits in size, it must be padded to the block size with zeroes on the most significant bytes. All 16 HMAC key registers must be written explicitly, as the core does not pad the HMAC key. Additionally, if the HMAC key is larger than 512 bits, the host is responsible for performing a preprocessing step to reduce it to one 512-bit block. This involves hashing the large key and padding the hash result with zeroes until it is 512 bits wide.

The (intermediate) result digest or MAC value can be read from these registers when the status register indicates that the operation is done, or suspended due to a context switch request (reading at other times results in all zeroes being returned). The MD5 result is available from digest registers A-D, the SHA-1 result from registers A-E, the SHA-224 final result from registers A-G, and the SHA-2 intermediate and SHA-256 final result from registers A-H.

The order of the bytes within the digest can be fed back unmodified into the little-endian data input when preprocessing HMAC keys larger than 64 bytes; or it can typically be inserted unmodified into a little-endian data stream (such as IPSEC packets), regardless of the selected algorithm.

The HMAC key itself cannot be read back from these registers, but is preserved for future processing as long as the SHAMD5_ODIGEST registers are not overwritten; this allows reuse of the HMAC key (without having to redo the HMAC key processing) for subsequent data blocks without having to reload it. This is done by setting HMAC key processing to 0 and Reuse HMAC key to 1 in the SHAMD5_MODE register.

19.2.9 SHAMD5_IDIGEST_A Register (Offset = 20h) [reset = 0h]

SHAMD5_IDIGEST_A is shown in Figure 19-13 and described in Table 19-20.

Return to Summary Table.

WRITE: Inner / Initial Digest [127:96] for MD5 [159:128] for SHA-1, [255:224] for SHA-2 / HMAC Key [287:256] for HMAC key proc

READ: Intermediate / Inner Digest [127:96] for MD5 [159:128] for SHA-1, [255:224] for SHA-2 /

Result Digest/MAC [127:96] for MD5 [159:128] for SHA-1, [223:192] for SHA-2 224, [255:224] for SHA-2 256

Figure 19-13 SHAMD5_IDIGEST_A Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-20 SHAMD5_IDIGEST_A Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.10 SHAMD5_IDIGEST_B Register (Offset = 24h) [reset = 0h]

SHAMD5_IDIGEST_B is shown in Figure 19-14 and described in Table 19-21.

Return to Summary Table.

WRITE: Inner / Initial Digest [95:64] for MD5 [127:96] for SHA-1, [223:192] for SHA-2 / HMAC Key [319:288] for HMAC key proc

READ: Intermediate / Inner Digest [95:64] for MD5 [127:96] for SHA-1, [223:192] for SHA-2 /

Result Digest/MAC [95:64] for MD5 [127:96] for SHA-1, [191:160] for SHA-2 224, [223:192] for SHA-2 256

Figure 19-14 SHAMD5_IDIGEST_B Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-21 SHAMD5_IDIGEST_B Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.11 SHAMD5_IDIGEST_C Register (Offset = 28h) [reset = 0h]

SHAMD5_IDIGEST_C is shown in Figure 19-15 and described in Table 19-22.

Return to Summary Table.

WRITE: Inner / Initial Digest [63:32] for MD5 [95:64] for SHA-1, [191:160] for SHA- 2 / HMAC Key [351:320] for HMAC key proc

READ: Intermediate / Inner Digest [63:32] for MD5 [95:64] for SHA-1, [191:160] for SHA-2 /

Result Digest/MAC [63:32] for MD5 [95:64] for SHA-1, [159:128] for SHA-2 224, [191:160] for SHA-2 256

Figure 19-15 SHAMD5_IDIGEST_C Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-22 SHAMD5_IDIGEST_C Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.12 SHAMD5_IDIGEST_D Register (Offset = 2Ch) [reset = 0h]

SHAMD5_IDIGEST_D is shown in Figure 19-16 and described in Table 19-23.

Return to Summary Table.

WRITE: Inner / Initial Digest [31:0] for MD5 [63:32] for SHA-1, [159:128] for SHA-2 / HMAC Key [383:352] for HMAC key proc

READ: Intermediate / Inner Digest [31:0] for MD5 [63:32] for SHA-1, [159:128] for SHA-2 /

Result Digest/MAC [31:0] for MD5 [63:32] for SHA-1, [127:96] for SHA-2 224, [159:128] for SHA-2 256

Figure 19-16 SHAMD5_IDIGEST_D Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-23 SHAMD5_IDIGEST_D Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.13 SHAMD5_IDIGEST_E Register (Offset = 30h) [reset = 0h]

SHAMD5_IDIGEST_E is shown in Figure 19-17 and described in Table 19-24.

Return to Summary Table.

WRITE: Inner / Initial Digest [31:0] for SHA-1, [127:96] for SHA-2 / HMAC Key [415:384] for HMAC key proc

READ: Intermediate / Inner Digest [31:0] for SHA-1, [127:96] for SHA-2 /

Result Digest/MAC [31:0] for SHA-1, [95:64] for SHA-2 224, [127:96] for SHA-2 256

Figure 19-17 SHAMD5_IDIGEST_E Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-24 SHAMD5_IDIGEST_E Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.14 SHAMD5_IDIGEST_F Register (Offset = 34h) [reset = 0h]

SHAMD5_IDIGEST_F is shown in Figure 19-18 and described in Table 19-25.

Return to Summary Table.

WRITE: Inner / Initial Digest [95:64] for SHA-2 / HMAC Key [447:416] for HMAC key proc

READ: Intermediate / Inner Digest [95:64] for SHA-2 /

Result Digest/MAC [63:32] for SHA-2 224, [95:64] for SHA-2 256

Figure 19-18 SHAMD5_IDIGEST_F Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-25 SHAMD5_IDIGEST_F Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.15 SHAMD5_IDIGEST_G Register (Offset = 38h) [reset = 0h]

SHAMD5_IDIGEST_G is shown in Figure 19-19 and described in Table 19-26.

Return to Summary Table.

WRITE: Inner / Initial Digest [63:32] for SHA-2 / HMAC Key [479:448] for HMAC key proc

READ: Intermediate / Inner Digest [63:32] for SHA-2 /

Result Digest/MAC [31:0] for SHA-2 224, [63:32] for SHA-2 256

Figure 19-19 SHAMD5_IDIGEST_G Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-26 SHAMD5_IDIGEST_G Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.16 SHAMD5_IDIGEST_H Register (Offset = 3Ch) [reset = 0h]

SHAMD5_IDIGEST_H is shown in Figure 19-20 and described in Table 19-27.

Return to Summary Table.

WRITE: Inner / Initial Digest [31:0] for SHA-2 / HMAC Key [511:480] for HMAC key proc

READ: Intermediate / Inner Digest [31:0] for SHA-2 /

Result Digest/MAC [31:0] for SHA-2 256

Figure 19-20 SHAMD5_IDIGEST_H Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-27 SHAMD5_IDIGEST_H Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.17 SHAMD5_DIGEST_COUNT Register (Offset = 40h) [reset = 0h]

SHAMD5_DIGEST_COUNT is shown in Figure 19-21 and described in Table 19-28.

Return to Summary Table.

WRITE: Initial Digest Count ([31:6] only, [5:0] assumed 0)

READ: Result / IntermediateDigest Count

The initial digest byte count for hash/HMAC continue operations (HMAC key processing = 0 and use algorithm constants = 0) on the secure world must be written to this register before starting the operation by writing to S_HASH_MODE. When either HMAC key processing is 1 or use algorithm constants is 1, this register does not need to be written, it is overwritten with 64 (1 hash block of key XOR ipad) or 0 respectively, automatically.

When starting an HMAC operation from pre-computes (HMAC key processing is 0), the value 64 must be written here to compensate for the appended key XOR ipad block. The value written should always be a 64 byte multiple; the lower 6 bits written are ignored.

The updated digest byte count (initial digest byte count plus bytes processed) can be read from this register when the status register indicates that the operation is done or suspended due to a context switch request, or when a secure world context out DMA is requested.

Figure 19-21 SHAMD5_DIGEST_COUNT Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-28 SHAMD5_DIGEST_COUNT Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

19.2.18 SHAMD5_MODE Register (Offset = 44h) [reset = X]

SHAMD5_MODE is shown in Figure 19-22 and described in Table 19-29.

Return to Summary Table.

Figure 19-22 SHAMD5_MODE Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
HMAC_OUTER_HASHRESERVEDHMAC_KEY_PROCCLOSE_HASHALGO_CONSTANTALGORESERVED
R/W-0hR-XR/W-0hR/W-0hR/W-0hR/W-0hR-X
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-29 SHAMD5_MODE Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7HMAC_OUTER_HASHR/W0h

The HMAC outer hash is performed on the hash digest when the inner hash has finished (block length exhausted and final hash performed if close_hash is 1). This bit should normally be set together with close_hash to finish the inner hash first, or block length should be zero (HMAC continues with the just outer hash to be done). Auto-cleared internally when outer hash performed.

0h = No operation

1h = HMAC processing

6RESERVEDRX
5HMAC_KEY_PROCR/W0h

Performs HMAC key processing on the 512-bit HMAC key loaded into the SHAMD5_IDIGEST_{A to H} and SHAMD5_ODIGEST_{A to H} register block. When HMAC key processing is finished, this bit is automatically cleared, and the resulting inner and outer digest is available from SHAMD5_IDIGEST_{A to H} and SHAMD5_ODIGEST_{A to H} respectively, after which regular hash processing (using SHAMD5_IDIGEST_{A to H} as initial digest) commences, until the block length is exhausted.

0h = No operation

1h = HMAC processing

4CLOSE_HASHR/W0h

Performs the padding; the hash/HMAC is closed at the end of the block, as per MD5/SHA-1/SHA-2 specification (that is, appropriate padding is added), or no padding is done, allowing the hash to be continued later. However, if the hash/HMAC is not closed, the block length must be a multiple of 64 bytes to ensure correct operation. Auto-cleared internally when hash closed.

0h = No padding, hash computation can be continued.

1h = Last packet is padded.

3ALGO_CONSTANTR/W0h

The initial digest register is overwritten with the algorithm constants for the selected algorithm when hashing, and the initial digest count register is reset to 0. This starts a normal hash operation. When continuing an existing hash or when performing an HMAC operation, this register must be set to 0 and the intermediate/inner digest or HMAC key and digest count must be written to the context input registers before writing SHAMD5_MODE. Auto-cleared internally after first block processed.

0h = Use pre-calculated digest (from another operation)

1h = Use constants of the selected algo.

2-1ALGOR/W0h

These bits select the hash algorithm to be used for processing.

0h = md5_128 algorithm

1h = sha1_160 algorithm

2h = sha2_224 algorithm

3h = sha2_256 algorithm

0RESERVEDRX

19.2.19 SHAMD5_LENGTH Register (Offset = 48h) [reset = 0h]

SHAMD5_LENGTH is shown in Figure 19-23 and described in Table 19-30.

Return to Summary Table.

WRITE: Block length / remaining byte count (bytes)

READ: Remaining byte count.

The value programmed must be a 64-byte multiple if close hash is set to 0. This register is also the trigger to start processing: once this register is written, the core commences requesting input data through DMA or IRQ (if programmed length > 0) and start processing.

The remaining byte count for the active operation can be read from this register when the interrupt status register indicates that the operation is suspended due to a context switch request.

Figure 19-23 SHAMD5_LENGTH Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-30 SHAMD5_LENGTH Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data

Hash Input Data Registers: The following are input data registers for the Hash/HMAC engine:

  • SHAMD5_DATA0_IN
  • SHAMD5_DATA1_IN
  • SHAMD5_DATA2_IN
  • SHAMD5_DATA3_IN
  • SHAMD5_DATA4_IN
  • SHAMD5_DATA5_IN
  • SHAMD5_DATA6_IN
  • SHAMD5_DATA7_IN
  • SHAMD5_DATA8_IN
  • SHAMD5_DATA9_IN
  • SHAMD5_DATA10_IN
  • SHAMD5_DATA11_IN
  • SHAMD5_DATA12_IN
  • SHAMD5_DATA13_IN
  • SHAMD5_DATA14_IN
  • SHAMD5_DATA15_IN

Writing 4-byte words to a word-aligned offset within this address range pushes the data into the 32-word deep (128 bytes = 1024 bits for one SHA-384/512 hash block) data-input FIFO. Although the actual address used within the range is not important, the order of the data words is. Also, do not exceed the FIFO size: check the status signals after writing a full block of 16 words or 32 words for SHA-384 and SHA-512.

This FIFO must be filled with 16 or 32 words (one full hash block) before the core can start processing the next block, except for the last hash block when close hash is set to 1. In this particular case, as many words need to be written as necessary to get the remaining bytes into the core. If the last word ends misaligned (the last word contains one or more invalid bytes) these bytes are ignored by the hash/HMAC engine. If a host writes additional words beyond the last hash data word of the current hash operation, the hash/HMAC engine ignores these additional words. Therefore, once the hash length decrements to zero, additional write to the data input FIFO are ignored. A new write to the length register allows the hash/HMAC engine to accept new data for storing into the data input FIFO.

A read from these registers (on any address in the address range) returns zeros.

19.2.20 SHAMD5_DATA0_IN Register (Offset = 80h) [reset = 0h]

SHAMD5_DATA0_IN is shown in Figure 19-24 and described in Table 19-31.

Return to Summary Table.

Data input message 0

Figure 19-24 SHAMD5_DATA0_IN Register
313029282726252423222120191817161514131211109876543210
DATA0_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-31 SHAMD5_DATA0_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA0_INR/W0h

Data

19.2.21 SHAMD5_DATA1_IN Register (Offset = 84h) [reset = 0h]

SHAMD5_DATA1_IN is shown in Figure 19-25 and described in Table 19-32.

Return to Summary Table.

Data input message 1

Figure 19-25 SHAMD5_DATA1_IN Register
313029282726252423222120191817161514131211109876543210
DATA1_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-32 SHAMD5_DATA1_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA1_INR/W0h

Data

19.2.22 SHAMD5_DATA2_IN Register (Offset = 88h) [reset = 0h]

SHAMD5_DATA2_IN is shown in Figure 19-26 and described in Table 19-33.

Return to Summary Table.

Data input message 2

Figure 19-26 SHAMD5_DATA2_IN Register
313029282726252423222120191817161514131211109876543210
DATA2_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-33 SHAMD5_DATA2_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA2_INR/W0h

Data

19.2.23 SHAMD5_DATA3_IN Register (Offset = 8Ch) [reset = 0h]

SHAMD5_DATA3_IN is shown in Figure 19-27 and described in Table 19-34.

Return to Summary Table.

Data input message 3

Figure 19-27 SHAMD5_DATA3_IN Register
313029282726252423222120191817161514131211109876543210
DATA3_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-34 SHAMD5_DATA3_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA3_INR/W0h

Data

19.2.24 SHAMD5_DATA4_IN Register (Offset = 90h) [reset = 0h]

SHAMD5_DATA4_IN is shown in Figure 19-28 and described in Table 19-35.

Return to Summary Table.

Data input message 4

Figure 19-28 SHAMD5_DATA4_IN Register
313029282726252423222120191817161514131211109876543210
DATA4_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-35 SHAMD5_DATA4_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA4_INR/W0h

Data

19.2.25 SHAMD5_DATA5_IN Register (Offset = 94h) [reset = 0h]

SHAMD5_DATA5_IN is shown in Figure 19-29 and described in Table 19-36.

Return to Summary Table.

Data input message 5

Figure 19-29 SHAMD5_DATA5_IN Register
313029282726252423222120191817161514131211109876543210
DATA5_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-36 SHAMD5_DATA5_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA5_INR/W0h

Data

19.2.26 SHAMD5_DATA6_IN Register (Offset = 98h) [reset = 0h]

SHAMD5_DATA6_IN is shown in Figure 19-30 and described in Table 19-37.

Return to Summary Table.

Data input message 6

Figure 19-30 SHAMD5_DATA6_IN Register
313029282726252423222120191817161514131211109876543210
DATA6_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-37 SHAMD5_DATA6_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA6_INR/W0h

Data

19.2.27 SHAMD5_DATA7_IN Register (Offset = 9Ch) [reset = 0h]

SHAMD5_DATA7_IN is shown in Figure 19-31 and described in Table 19-38.

Return to Summary Table.

Data input message 7

Figure 19-31 SHAMD5_DATA7_IN Register
313029282726252423222120191817161514131211109876543210
DATA7_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-38 SHAMD5_DATA7_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA7_INR/W0h

Data

19.2.28 SHAMD5_DATA8_IN Register (Offset = A0h) [reset = 0h]

SHAMD5_DATA8_IN is shown in Figure 19-32 and described in Table 19-39.

Return to Summary Table.

Data input message 8

Figure 19-32 SHAMD5_DATA8_IN Register
313029282726252423222120191817161514131211109876543210
DATA8_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-39 SHAMD5_DATA8_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA8_INR/W0h

Data

19.2.29 SHAMD5_DATA9_IN Register (Offset = A4h) [reset = 0h]

SHAMD5_DATA9_IN is shown in Figure 19-33 and described in Table 19-40.

Return to Summary Table.

Data input message 9

Figure 19-33 SHAMD5_DATA9_IN Register
313029282726252423222120191817161514131211109876543210
DATA9_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-40 SHAMD5_DATA9_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA9_INR/W0h

Data

19.2.30 SHAMD5_DATA10_IN Register (Offset = A8h) [reset = 0h]

SHAMD5_DATA10_IN is shown in Figure 19-34 and described in Table 19-41.

Return to Summary Table.

Data input message 10

Figure 19-34 SHAMD5_DATA10_IN Register
313029282726252423222120191817161514131211109876543210
DATA10_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-41 SHAMD5_DATA10_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA10_INR/W0h

Data

19.2.31 SHAMD5_DATA11_IN Register (Offset = ACh) [reset = 0h]

SHAMD5_DATA11_IN is shown in Figure 19-35 and described in Table 19-42.

Return to Summary Table.

Data input message 11

Figure 19-35 SHAMD5_DATA11_IN Register
313029282726252423222120191817161514131211109876543210
DATA11_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-42 SHAMD5_DATA11_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA11_INR/W0h

Data

19.2.32 SHAMD5_DATA12_IN Register (Offset = B0h) [reset = 0h]

SHAMD5_DATA12_IN is shown in Figure 19-36 and described in Table 19-43.

Return to Summary Table.

Data input message 12

Figure 19-36 SHAMD5_DATA12_IN Register
313029282726252423222120191817161514131211109876543210
DATA12_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-43 SHAMD5_DATA12_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA12_INR/W0h

Data

19.2.33 SHAMD5_DATA13_IN Register (Offset = B4h) [reset = 0h]

SHAMD5_DATA13_IN is shown in Figure 19-37 and described in Table 19-44.

Return to Summary Table.

Data input message 13

Figure 19-37 SHAMD5_DATA13_IN Register
313029282726252423222120191817161514131211109876543210
DATA13_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-44 SHAMD5_DATA13_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA13_INR/W0h

Data

19.2.34 SHAMD5_DATA14_IN Register (Offset = B8h) [reset = 0h]

SHAMD5_DATA14_IN is shown in Figure 19-38 and described in Table 19-45.

Return to Summary Table.

Data input message 14

Figure 19-38 SHAMD5_DATA14_IN Register
313029282726252423222120191817161514131211109876543210
DATA14_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-45 SHAMD5_DATA14_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA14_INR/W0h

Data

19.2.35 SHAMD5_DATA15_IN Register (Offset = BCh) [reset = 0h]

SHAMD5_DATA15_IN is shown in Figure 19-39 and described in Table 19-46.

Return to Summary Table.

Data input message 15

Figure 19-39 SHAMD5_DATA15_IN Register
313029282726252423222120191817161514131211109876543210
DATA15_IN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-46 SHAMD5_DATA15_IN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATA15_INR/W0h

Data

19.2.36 SHAMD5_SYSCONFIG Register (Offset = 110h) [reset = X]

SHAMD5_SYSCONFIG is shown in Figure 19-40 and described in Table 19-47.

Return to Summary Table.

Figure 19-40 SHAMD5_SYSCONFIG Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDPCONT_SWTRESERVEDPDMA_ENPIT_ENRESERVED
R-XR/W-0hR-XR/W-0hR/W-0hR-X
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-47 SHAMD5_SYSCONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDRX
6PCONT_SWTR/W0h

Finishes all pending data and context DMA input requests (but will not assert any new requests), finishes processing all data in the module, and provides a saved context (partial hash result, updated digest count, remaining length, updated mode information where applicable) for the last operation that was interrupted, so that it can be resumed later.

5-4RESERVEDRX
3PDMA_ENR/W0h

Enable DMA

0h = DMA disabled

1h = DMA enabled

2PIT_ENR/W0h

Enable Interrupt

0h = Interrupt disabled

1h = Interrupt enabled

1-0RESERVEDRX

19.2.37 SHAMD5_IRQSTATUS Register (Offset = 118h) [reset = X]

SHAMD5_IRQSTATUS is shown in Figure 19-41 and described in Table 19-48.

Return to Summary Table.

Figure 19-41 SHAMD5_IRQSTATUS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDCONTEXT_READYPARTHASH_READYINPUT_READYOUTPUT_READY
R-XRO-1hRO-0hRO-0hRO-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-48 SHAMD5_IRQSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3CONTEXT_READYRO1h

Indicates that the secure-side context input registers are available for a new context for the next packet to be processed.

2PARTHASH_READYRO0h

After a secure-side context switch request, this bit reads as 1, indicating that the saved context is available from the secure-side context output registers. If the context switch request coincides with a final hash (when hashing) or an outer hash (when doing HMAC), that PartHashReady will not become active, but a regular output ready occurs instead (indicating that the result is final and therefore no continuation is required).

1INPUT_READYRO0h

Indicates that the secure-side data FIFO is ready to receive the next 64-byte data block.

0OUTPUT_READYRO0h

Indicates that a (partial) result or saved context is available from the secure-side context output registers.

19.2.38 SHAMD5_IRQENABLE Register (Offset = 11Ch) [reset = X]

SHAMD5_IRQENABLE is shown in Figure 19-42 and described in Table 19-49.

Return to Summary Table.

The SHAMD5_IRQENABLE register contains an enable bit for each unique interrupt for the public side. An interrupt is enabled when both the global enable in SHAMD5_SYSCONFIG (PIT_en) and the bit in this register are both set to 1. An interrupt that is enabled is propagated to the SINTREQUEST_P output. The dedicated partial hash output (SINTREQUEST_PART_P) is not affected by this register, it is only affected by the global enable SHAMD5_SYSCONFIG (PIT_en).

Figure 19-42 SHAMD5_IRQENABLE Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDM_CONTEXT_READYM_PARTHASH_READYM_INPUT_READYM_OUTPUT_READY
R-XR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-49 SHAMD5_IRQENABLE Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3M_CONTEXT_READYR/W0h

Mask for context ready

2M_PARTHASH_READYR/W0h

Mask for partial hash

1M_INPUT_READYR/W0h

Mask for input_ready

0M_OUTPUT_READYR/W0h

Mask for output_ready

19.2.39 DTHE_SHA_IM Register (Offset = 810h) [reset = X]

DTHE_SHA_IM is shown in Figure 19-43 and described in Table 19-50.

Return to Summary Table.

SHA/MD5 interrupt mask set register that allows the control of which interrupt source should interrupt the processor.

Figure 19-43 DTHE_SHA_IM Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDDinCoutCin
R-XR/W-1hR/W-1hR/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-50 DTHE_SHA_IM Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDRX
2DinR/W1h

Data in: this interrupt is raised when DMA writes last word of input data to internal FIFO of the engine.

1CoutR/W1h

Context out: this interrupt is raised when DMA completes the output context movement from internal register.

0CinR/W1h

Context in: this interrupt is raised when DMA completes a context write to internal register

19.2.40 DTHE_SHA_RIS Register (Offset = 814h) [reset = X]

DTHE_SHA_RIS is shown in Figure 19-44 and described in Table 19-51.

Return to Summary Table.

SHAMD5 raw interrupt status register

Figure 19-44 DTHE_SHA_RIS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDDinCoutCin
R-XR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-51 DTHE_SHA_RIS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDRX
2DinR0h

Input data movement is done

1CoutR0h

Context output is done

0CinR0h

Context input is done

19.2.41 DTHE_SHA_MIS Register (Offset = 818h) [reset = X]

DTHE_SHA_MIS is shown in Figure 19-45 and described in Table 19-52.

Return to Summary Table.

SHAMD5 masked interrupt status register.

Figure 19-45 DTHE_SHA_MIS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDDinCoutCin
R-XR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-52 DTHE_SHA_MIS Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDRX
2DinR0h

Input data movement is done

1CoutR0h

Context output is done

0CinR0h

Context input is done

19.2.42 DTHE_SHA_IC Register (Offset = 81Ch) [reset = X]

DTHE_SHA_IC is shown in Figure 19-46 and described in Table 19-53.

Return to Summary Table.

SHAMD5 interrupt acknowledge register. Writing 1 to these bits clear the status flag in RIS and MIS register. Reads are always zero.

Figure 19-46 DTHE_SHA_IC Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDDinCoutCin
R-XR/WC-0hWC-0hWC-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-53 DTHE_SHA_IC Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDRX
2DinR/WC0h

Clear “input data movement done” flag

1CoutWC0h

Clear “output done” flag

0CinWC0h

Clear “input done” flag