SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

7.3 I2C Registers

Table 7-3 lists the memory-mapped registers for the I2C. All register offset addresses not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.

All addresses given are relative to the I2C base address: 0x4002.0000.

The I2C module clock must be enabled before the registers can be programmed. There must be a delay of three system clocks after the I2C module clock is enabled before any I2C module registers are accessed.

The hw_i2c.h file in the TivaWare Driver Library uses a base address of 0x800 for the I2C slave registers. Be aware when using registers with offsets from 0x800 to 0x818 that TivaWare for E Series uses an offset from 0x000 to 0x018 with the slave base address.

Table 7-3 I2C Registers
OffsetAcronymRegister NameSection
0hI2CMSAI2C Master Slave AddressSection 7.3.1
4hI2CMCSI2C Master Control/StatusSection 7.3.2
8hI2CMDRI2C Master DataSection 7.3.3
ChI2CMTPRI2C Master Timer PeriodSection 7.3.4
10hI2CMIMRI2C Master Interrupt MaskSection 7.3.5
14hI2CMRISI2C Master Control/StatusSection 7.3.6
18hI2CMMISI2C Master Masked Interrupt StatusSection 7.3.7
1ChI2CMICRI2C Master Interrupt ClearSection 7.3.8
20hI2CMCRI2C Master ConfigurationSection 7.3.9
24hI2CMCLKOCNTI2C Master Clock Low Timeout CountSection 7.3.10
2ChI2CMBMONI2C Master Bus MonitorSection 7.3.11
30hI2CMBLENI2C Master Burst LengthSection 7.3.12
34hI2CMBCNTI2C Master Burst CountSection 7.3.13
800hI2CSOARI2C Slave Own AddressSection 7.3.14
804hI2CSCSRI2C Slave Control/StatusSection 7.3.15
808hI2CSDRI2C Slave DataSection 7.3.16
80ChI2CSIMRI2C Slave Interrupt MaskSection 7.3.17
810hI2CSRISI2C Slave Raw Interrupt StatusSection 7.3.18
814hI2CSMISI2C Slave Masked Interrupt StatusSection 7.3.19
818hI2CSICRI2C Slave Interrupt ClearSection 7.3.20
81ChI2CSOAR2I2C Slave Own Address 2Section 7.3.21
820hI2CSACKCTLI2C Slave ACK ControlSection 7.3.22
F00hI2CFIFODATAI2C FIFO DataSection 7.3.23
F04hI2CFIFOCTLI2C FIFO ControlSection 7.3.24
F08hI2CFIFOSTATUSI2C FIFO StatusSection 7.3.25
FC0hI2CPPI2C Peripheral PropertiesSection 7.3.26
FC4hI2CPCI2C Peripheral ConfigurationSection 7.3.27

7.3.1 I2CMSA Register (Offset = 0h) [reset = 0h]

I2CMSA is shown in Figure 7-14 and described in Table 7-4.

Return to Summary Table.

This register consists of 8 bits: 7 address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (high), or Transmit (low).

Figure 7-14 I2CMSA Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSAR_S
R-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-4 I2CMSA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-1SAR/W0h

I2C Slave Address

This field specifies bits A6 through A0 of the slave address.

0R_SR/W0h

Receive/Send

The R/S bit specifies if the next master operation is a Receive (High) or Transmit (Low).

0h = Transmit

1h = Receive

7.3.2 I2CMCS Register (Offset = 4h) [reset = 20h]

I2CMCS is shown in Figure 7-15 and described in Table 7-5.

Return to Summary Table.

Figure 7-15 I2CMCS Register
3130292827262524
ACTDMARXACTDMATXRESERVED
R/W-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CLKTOBUSBSY_OR_BURSTIDLE_OR_QCMDARBLST_OR_HSDATACK_OR_ACKADRACK_OR_STOPERROR_OR_STARTBUSY_OR_RUN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-5 I2CMCS Register Field Descriptions
BitFieldTypeResetDescription
31ACTDMARXR/W0h

DMA RX Active Status

0h (R) = DMA RX is not active

1h (R) = DMA RX is active

30ACTDMATXR0h

DMA TX Active Status

0h (R) = DMA TX is not active

1h (R) = DMA TX is active.

29-8RESERVEDR0h
7CLKTOR/W0h

Clock Timeout Error

This bit is cleared when the master sends a STOP condition or if the I2C master is reset.

0h (R) = No clock time-out error.

1h (R) = The clock time-out error has occurred.

6BUSBSY_OR_BURSTR/W0h

Bus Busy (R) or Burst Enable (W)

The bit changes based on the START and STOP conditions.

0h (W) = Burst operation is disabled.

0h (R) = The I2C bus is idle.

1h (W) = The master is enabled to burst using the receive and transmit FIFOs.

1h (R) = The I2C bus is busy.

Note that the BURST and RUN bits are mutually exclusive.

5IDLE_OR_QCMDR/W1h

I2C Idle (R) or Quick Command (W)

To execute a quick command, the START, STOP and RUN bits must also be set. After the quick command is issued, the master generates a STOP.

0h (W) = Bus transaction is not a quick command.

0h (R) = The I2C controller is not idle.

1h (W) = The bus transaction is a quick command.

1h (R) = The I2C controller is idle.

4ARBLST_OR_HSR/W0h

Arbitration Lost (R) or Reserved (High-Speed Enable Not Supported) (W)

0h (W) = The master operates in Standard or Fast mode as selected by using a value in the I2CMTPR register that results in an SCL frequency of 100 kbps for standard mode, or 400 kbps for fast mode.

0h (R) = The I2C controller won arbitration.

1h (R) = The I2C controller lost arbitration.

3DATACK_OR_ACKR/W0h

Acknowledge Data (R) or Data Acknowledge Enable (W)

0h (W) = The received data byte is not acknowledged automatically by the master.

0h (R) = The transmitted data was acknowledged

1h (W) = The received data byte is acknowledged automatically by the master.

1h (R) = The transmitted data was not acknowledged.

2ADRACK_OR_STOPR/W0h

Acknowledge Address (R) or Generate STOP (W)

0h (W) = The controller does not generate the STOP condition.

0h (R) = The transmitted address was acknowledged

1h (W) = The controller generates the STOP condition.

1h (R) = The transmitted address was not acknowledged.

1ERROR_OR_STARTR/W0h

Error (R) or Generate START (W)

The error can be when the slave address is not acknowledged, or when the transmit data is not acknowledged.

0h (W) = The controller does not generate the START condition.

0h (R) = No error was detected on the last operation.

1h (W) = The controller generates the START or repeated START condition.

1h (R) = An error occurred on the last operation.

0BUSY_OR_RUNR/W0h

I2C Busy (R) or I2C Master Enable (W)

When the BUSY bit is set, the other status bits are not valid. Note that the BURST and RUN bits are mutually exclusive.

0h (W) = In standard mode, this encoding means the master is unable to transmit or receive data. In Burst mode, this bit is not used and must be set to 0.

0h (R) = The controller is idle.

1h (W) = The master is able to transmit or receive data. Note that this bit cannot be set in burst mode.

1h (R) = The controller is busy.

Table 7-6 Write Field Decoding for I2CMCS[6:0]
Current StateI2CMSA[0]I2CMCS[6:0]Next State Description
R/SBURSTQCCMDHSACKSTOPSTARTRUN
Idle0000X(1)011START condition followed by TRANSMIT (master goes to Master Transmit state).
0000X111START condition followed by a TRANSMIT and STOP condition (master remains in Idle state).
0100X010START condition followed by N FIFO-serviced TRANSMITs (master goes to Master Transmit state).
0100X110START condition followed by N FIFO-serviced TRANSMITs and STOP condition (master remains in Idle state).
10000011START condition followed by RECEIVE operation with negative ACK (master goes to Master Receive state).
00100111Quick Command (Send). After Quick Command is executed, the master returns to Idle state.
10100111Quick Command (Receive). After Quick Command is executed, the master returns to Idle state.
10000111START condition followed by RECEIVE and STOP condition (master remains in Idle state).
10001011START condition followed by RECEIVE (master goes to Master Receive state).
11000010START condition followed by N FIFO-serviced RECEIVE operations with a negative ACK on the last RECEIVE operation (master goes to Master Receive state).
11000110START condition followed by N FIFO-serviced RECEIVE operations with a negative ACK on the last RECEIVE and STOP condition (master remains in Idle state).
11001010START condition followed by N FIFO-serviced RECEIVE operations (master goes to Master Receive state).
00010011START/RUN condition where master byte is sent with no ACK; followed by High-Speed transmit Operation. All subsequent transfers are carried out using normal transmit commands.
01010000RUN/BURST condition where master byte is sent with no ACK; followed by High-Speed Burst transmit Operation.
10001111Illegal
10001110Illegal
Master TransmitX000X001TRANSMIT operation (master remains in Master Transmit state).
X000X100STOP condition (master goes to Idle state).
X000X101TRANSMIT followed by STOP condition (master goes to Idle state).
X100X000N FIFO-serviced TRANSMIT operations (master remains in Master Transmit state).
X100X100N FIFO-serviced TRANSMIT operations followed by STOP condition (master goes to Idle state).
0000X011Repeated START condition followed by a TRANSMIT operation (master remains in Master Transmit state).
0000X111Repeated START condition followed by TRANSMIT and STOP condition (master goes to Idle state).
0100X010Repeated START condition followed by N FIFO-serviced TRANSMIT operations (master remains in Master Transmit state).
0100X110Repeated START condition followed by N FIFO-serviced TRANSMIT operations and STOP condition (master goes to Idle state).
10000011Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive state).
10000111Repeated START condition followed by a RECEIVE and STOP condition (master goes to Idle state).
10001011Repeated START condition followed by RECEIVE operation (master goes to Master Receive state).
11000010Repeated START condition followed by N FIFO-serviced RECEIVE operations with a negative ACK on the last RECEIVE operation (master goes to Master Receive state).
11000110Repeated START condition followed by N FIFO-serviced RECEIVE operations and STOP condition (master goes to Idle state).
11001010Repeated START condition followed by N FIFO-serviced RECEIVE operations (master goes to Master Receive state).
10001111Illegal
11001110Illegal
Master ReceiveX0000001RECEIVE operation with negative ACK (master remains in Master Receive state).
X000X100STOP condition (master goes to Idle state).(2)
X0000101RECEIVE operation followed by STOP condition (master goes to Idle state).
X0001001RECEIVE operation (master remains in Master Receive state).
X1000000N FIFO-serviced RECEIVE operations with negative ACK on the last RECEIVE (master remains in Master Receive state).
X1000100N FIFO-serviced RECEIVE operations followed by STOP condition (master goes to Idle state).
X1001000N FIFO-serviced RECEIVE operations (master remains in Master Receive state).
X0001101Illegal
X1001100Illegal
10000011Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receive state).
10000111Repeated START condition followed by RECEIVE and STOP condition (master goes to Idle state).
10001011Repeated START condition followed by RECEIVE operation (master remains in Master Receive state).
11000010Repeated START condition followed by N FIFO-serviced RECEIVE operations with a negative ACK on the last RECEIVE operation (master remains in Master Receive state).
11000110Repeated START condition followed by N FIFO-serviced RECEIVE operations and STOP condition (master goes to Idle state).
11001010Repeated START condition followed by N FIFO-serviced RECEIVE operations (master remains in Master Receive state).
0000X011Repeated START condition followed by TRANSMIT operation (master goes to Master Transmit state).
0000X111Repeated START condition followed by TRANSMIT and STOP condition (master goes to Idle state).
0100X010Repeated START condition followed by N FIFO-serviced TRANSMIT operations (master goes to Master Transmit state).
0100X110Repeated START condition followed by N FIFO-serviced TRANSMIT operations and STOP condition (master goes to Idle state).
All other combinations not listed are nonoperations.NOP
(1) An X in a table cell indicates the bit can be 0 or 1.
(2) In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master, or an Address Negative Acknowledge executed by the slave.

7.3.3 I2CMDR Register (Offset = 8h) [reset = 0h]

I2CMDR is shown in Figure 7-16 and described in Table 7-7.

Return to Summary Table.

This register contains the data to be transmitted when in the master transmit state and the data received when in the master receive state. If the BURST bit is enabled in the I2CMCS register, then the I2CFIFODATA register is used for the current data transmit or receive value and this register is ignored.

Note:

This register is read-sensitive. See the register description for details.

Figure 7-16 I2CMDR Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-7 I2CMDR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0DATAR/W0h

This byte contains the data transferred during a transaction.

7.3.4 I2CMTPR Register (Offset = Ch) [reset = 1h]

I2CMTPR is shown in Figure 7-17 and described in Table 7-8.

Return to Summary Table.

This register is programmed to set the timer period for the SCL clock and assign the SCL clock to standard.

Figure 7-17 I2CMTPR Register
31302928272625242322212019181716
RESERVEDPULSEL
R-0hR/W-0h
1514131211109876543210
RESERVEDTPR
R-0hR/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-8 I2CMTPR Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0h
18-16PULSELR/W0h

Glitch Suppression Pulse Width

This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of system clocks.

0h = Bypass

1h = 1 clock

2h = 2 clocks

3h = 3 clocks

4h = 4 clocks

5h = 8 clocks

6h = 16 clocks

7h = 31 clocks

15-7RESERVEDR0h
6-0TPRR/W1h

Timer Period

This field is used in the equation to configure

SCL_PERIOD: SCL_PERIOD = 2 -(1 + TPR) -(SCL_LP + SCL_HP) -CLK_PRD

where:

SCL_PRD is the SCL line period (I2C clock)

TPR is the Timer Period register value (range of 1 to 127)

SCL_LP is the SCL Low period (fixed at 6)

SCL_HP is the SCL High period (fixed at 4)

CLK_PRD is the system clock period in ns.

7.3.5 I2CMIMR Register (Offset = 10h) [reset = 0h]

I2CMIMR is shown in Figure 7-18 and described in Table 7-9.

Return to Summary Table.

This register controls whether a raw interrupt is promoted to a controller interrupt.

Figure 7-18 I2CMIMR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRXFFIMTXFEIMRXIMTXIM
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
ARBLOSTIMSTOPIMSTARTIMNACKIMDMATXIMDMARXIMCLKIMIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-9 I2CMIMR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11RXFFIMR/W0h

Receive FIFO Full Interrupt Mask

0h = The RXFFRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The Receive FIFO Full interrupt is sent to the interrupt controller when the RXFFRIS bit in the I2CMRIS register is set.

10TXFEIMR/W0h

Transmit FIFO Empty Interrupt Mask

Note: The TXFEIM interrupt mask bit in the I2CMIMR register should be clear (masking the TXFE interrupt) when the master is performing an RX Burst from the RXFIFO and should be unmasked before starting a TX FIFO transfers.

0h = The TXFERIS interrupt is suppressed and not sent to the interrupt controller.

1h = The Transmit FIFO Empty interrupt is sent to the interrupt controller when the TXFERIS bit in the I2CMRIS register is set.

9RXIMR/W0h

Receive FIFO Request Interrupt Mask

0h = The RXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The RX FIFO Request interrupt is sent to the interrupt controller when the RXRIS bit in the I2CMRIS register is set.

8TXIMR/W0h

Transmit FIFO Request Interrupt Mask

0h = The TXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CMRIS register is set.

7ARBLOSTIMR/W0h

Transmit FIFO Request Interrupt Mask

0h = The TXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CMRIS register is set.

6STOPIMR/W0h

STOP Detection Interrupt Mask

0h = The STOPRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The STOP detection interrupt is sent to the interrupt controller when the STOPRIS bit in the I2CMRIS register is set.

5STARTIMR/W0h

START Detection Interrupt Mask

0h = The STARTRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The START detection interrupt is sent to the interrupt controller when the STARTRIS bit in the I2CMRIS register is set.

4NACKIMR/W0h

Address/Data NACK Interrupt Mask

0h = The NACKRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The address/data NACK interrupt is sent to the interrupt controller when the NACKRIS bit in the I2CMRIS register is set.

3DMATXIMR/W0h

Transmit DMA Interrupt Mask

0h = The DMATXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The transmit DMA complete interrupt is sent to the interrupt controller when the DMATXRIS bit in the I2CMRIS register is set.

2DMARXIMR/W0h

Receive DMA Interrupt Mask

0h = The DMARXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The receive DMA complete interrupt is sent to the interrupt controller when the DMARXRIS bit in the I2CMRIS register is set.

1CLKIMR/W0h

Clock Timeout Interrupt Mask

0h = The CLKRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The clock timeout interrupt is sent to the interrupt controller when the CLKRIS bit in the I2CMRIS register is set.

0IMR/W0h

Master Interrupt Mask

0h = The RIS interrupt is suppressed and not sent to the interrupt controller.

1h = The master interrupt is sent to the interrupt controller when the RIS bit in the I2CMRIS register is set.

7.3.6 I2CMRIS Register (Offset = 14h) [reset = 0h]

I2CMRIS is shown in Figure 7-19 and described in Table 7-10.

Return to Summary Table.

This register specifies whether an interrupt is pending.

Figure 7-19 I2CMRIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRXFFRISTXFERISRXRISTXRIS
R-0hR-0hR-0hR-0hR-0h
76543210
ARBLOSTRISSTOPRISSTARTRISNACKRISDMATXRISDMARXRISCLKRISRIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-10 I2CMRIS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11RXFFRISR0h

Receive FIFO Full Raw Interrupt Status

This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR register.

0h = No interrupt

1h = The Receive FIFO Full interrupt is pending.

10TXFERISR0h

Transmit FIFO Empty Raw Interrupt Status

This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR register.

0h = No interrupt

1h = The Transmit FIFO Empty interrupt is pending.

Note that if the TXFERIS interrupt is cleared (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert, even though the TX FIFO remains empty in this situation.

9RXRISR0h

Receive FIFO Request Raw Interrupt Status

This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register.

0h = No interrupt

1h = The trigger level for the RX FIFO has been reached or there is data in the FIFO and the burst count is zero. Thus, a RX FIFO request interrupt is pending.

8TXRISR0h

Transmit Request Raw Interrupt Status

This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register.

0h = No interrupt

1h = The trigger level for the TX FIFO has been reached and more data is needed to complete the burst. Thus, a TX FIFO request interrupt is pending.

7ARBLOSTRISR0h

Arbitration Lost Raw Interrupt Status

This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register.

0h = No interrupt

1h = The Arbitration Lost interrupt is pending.

6STOPRISR0h

STOP Detection Raw Interrupt Status

This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR register.

0h = No interrupt

1h = The STOP Detection interrupt is pending.

5STARTRISR0h

START Detection Raw Interrupt Status

This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR register.

0h = No interrupt

1h = The START Detection interrupt is pending.

4NACKRISR0h

Address/Data NACK Raw Interrupt Status

This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR register.

0h = No interrupt

1h = The address/data NACK interrupt is pending.

3DMATXRISR0h

Transmit DMA Raw Interrupt Status

This bit is cleared by writing a 1 to the DMATXIC bit in the I2CMICR register.

0h = No interrupt.

1h = The transmit DMA complete interrupt is pending.

2DMARXRISR0h

Receive DMA Raw Interrupt Status

This bit is cleared by writing a 1 to the DMARXIC bit in the I2CMICR register.

0h = No interrupt.

1h = The receive DMA complete interrupt is pending.

1CLKRISR0h

Clock Timeout Raw Interrupt Status

This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.

0h = No interrupt.

1h = The clock timeout interrupt is pending.

0RISR0h

Master Raw Interrupt Status

This interrupt includes:

Master transaction completed

Next byte transfer request

This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.

0h = No interrupt.

1h = A master interrupt is pending.

7.3.7 I2CMMIS Register (Offset = 18h) [reset = 0h]

I2CMMIS is shown in Figure 7-20 and described in Table 7-11.

Return to Summary Table.

This register specifies whether an interrupt was signaled.

Figure 7-20 I2CMMIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRXFFMISTXFEMISRXMISTXMIS
R-0hR-0hR-0hR-0hR-0h
76543210
ARBLOSTMISSTOPMISSTARTMISNACKMISDMATXMISDMARXMISCLKMISMIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-11 I2CMMIS Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11RXFFMISR0h

Receive FIFO Full Interrupt Mask

This bit is cleared by writing a 1 to the RXFFIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked Receive FIFO Full interrupt was signaled and is pending.

10TXFEMISR0h

Transmit FIFO Empty Interrupt Mask

This bit is cleared by writing a 1 to the TXFEIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked Transmit FIFO Empty interrupt was signaled and is pending.

9RXMISR0h

Receive FIFO Request Interrupt Mask

This bit is cleared by writing a 1 to the RXIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked Receive FIFO Request interrupt was signaled and is pending.

8TXMISR0h

Transmit Request Interrupt Mask

This bit is cleared by writing a 1 to the TXIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked Transmit FIFO Request interrupt was signaled and is pending.

7ARBLOSTMISR0h

Arbitration Lost Interrupt Mask

This bit is cleared by writing a 1 to the ARBLOSTIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked Arbitration Lost interrupt was signaled and is pending.

6STOPMISR0h

STOP Detection Interrupt Mask

This bit is cleared by writing a 1 to the STOPIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked STOP Detection interrupt was signaled and is pending.

5STARTMISR0h

START Detection Interrupt Mask

This bit is cleared by writing a 1 to the STARTIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked START Detection interrupt was signaled and is pending.

4NACKMISR0h

Address/Data NACK Interrupt Mask

This bit is cleared by writing a 1 to the NACKIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked Address/Data NACK interrupt was signaled and is pending.

3DMATXMISR0h

Transmit DMA Interrupt Status

This bit is cleared by writing a 1 to the DMATXIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked transmit DMA complete interrupt was signaled and is pending.

2DMARXMISR0h

Receive DMA Interrupt Status

This bit is cleared by writing a 1 to the DMARXIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked receive DMA complete interrupt was signaled and is pending.

1CLKMISR0h

Clock Timeout Masked Interrupt Status

This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked clock timeout interrupt was signaled and is pending.

0MISR0h

Clock Timeout Masked Interrupt Status

This bit is cleared by writing a 1 to the CLKIC bit in the I2CMICR register.

0h = No interrupt.

1h = An unmasked clock timeout interrupt was signaled and is pending.

7.3.8 I2CMICR Register (Offset = 1Ch) [reset = 0h]

I2CMICR is shown in Figure 7-21 and described in Table 7-12.

Return to Summary Table.

This register clears the raw and masked interrupts.

Figure 7-21 I2CMICR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRXFFICTXFEICRXICTXIC
R-0hW-0hW-0hW-0hW-0h
76543210
ARBLOSTICSTOPICSTARTICNACKICDMATXICDMARXICCLKCICIC
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-12 I2CMICR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11RXFFICW0h

Receive FIFO Full Interrupt Clear

Writing a 1 to this bit clears the RXFFIS bit in the I2CMRIS register and the RXFFMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

10TXFEICW0h

Transmit FIFO Empty Interrupt Clear

Writing a 1 to this bit clears the TXFERIS bit in the I2CMRIS register and the TXFEMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

9RXICW0h

Receive FIFO Request Interrupt Clear

Writing a 1 to this bit clears the RXRIS bit in the I2CMRIS register and the RXMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

8TXICW0h

Transmit FIFO Request Interrupt Clear

Writing a 1 to this bit clears the TXRIS bit in the I2CMRIS register and the TXMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

7ARBLOSTICW0h

Arbitration Lost Interrupt Clear

Writing a 1 to this bit clears the ARBLOSTRIS bit in the I2CMRIS register and the ARBLOSTMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

6STOPICW0h

STOP Detection Interrupt Clear

Writing a 1 to this bit clears the STOPRIS bit in the I2CMRIS register and the STOPMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

5STARTICW0h

START Detection Interrupt Clear

Writing a 1 to this bit clears the STARTRIS bit in the I2CMRIS register and the STARTMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

4NACKICW0h

Address/Data NACK Interrupt Clear

Writing a 1 to this bit clears the NACKRIS bit in the I2CMRIS register and the NACKMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

3DMATXICW0h

Transmit DMA Interrupt Clear

Writing a 1 to this bit clears the DMATXRIS bit in the I2CMRIS register and the DMATXMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

2DMARXICW0h

Receive DMA Interrupt Clear

Writing a 1 to this bit clears the DMARXRIS bit in the I2CMRIS register and the DMARXMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

1CLKCICW0h

Clock Timeout Interrupt Clear

Writing a 1 to this bit clears the CLKRIS bit in the I2CMRIS register and the CLKMIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

0ICW0h

Master Interrupt Clear

Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the MIS bit in the I2CMMIS register.

A read of this register returns no meaningful data.

7.3.9 I2CMCR Register (Offset = 20h) [reset = 0h]

I2CMCR is shown in Figure 7-22 and described in Table 7-13.

Return to Summary Table.

This register configures the mode (master or slave), and sets the interface for test mode loopback.

Figure 7-22 I2CMCR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSFEMFERESERVEDLPBK
R-0hR/W-0hR/W-0hR-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-13 I2CMCR Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5SFER/W0h

I2C Slave Function Enable

0h = Slave mode is disabled.

1h = Slave mode is enabled.

4MFER/W0h

I2C Master Function Enable

0h = Master mode is disabled.

1h = Master mode is enabled.

3-1RESERVEDR0h
0LPBKR/W0h

I2C Loopback

0h = Normal operation.

1h = The controller in a test mode loopback configuration.

7.3.10 I2CMCLKOCNT Register (Offset = 24h) [reset = 0h]

I2CMCLKOCNT is shown in Figure 7-23 and described in Table 7-14.

Return to Summary Table.

This register contains the upper 8 bits of a 12-bit counter that can be used to keep the timeout limit for clock stretching by a remote slave. The lower four bits of the counter are not user visible and are always 0x0.

Note:

The master clock low timeout counter counts for the entire time SCL is held Low continuously. If SCL is de-asserted at any point, the master clock low timeout counter is reloaded with the value in the I2CMCLKOCNT register and begins counting down from this value.

Figure 7-23 I2CMCLKOCNT Register
313029282726252423222120191817161514131211109876543210
RESERVEDCNTL
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-14 I2CMCLKOCNT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0CNTLR/W0h

I2C Master Count

This field contains the upper 8 bits of a 12-bit counter for the clock low timeout count.

Note: The value of CNTL must be greater than 0x1.

7.3.11 I2CMBMON Register (Offset = 2Ch) [reset = 3h]

I2CMBMON is shown in Figure 7-24 and described in Table 7-15.

Return to Summary Table.

This register is used to determine the SCL and SDA signal status.

Figure 7-24 I2CMBMON Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDSDASCL
R-0hR-1hR-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-15 I2CMBMON Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1SDAR1h

I2C SDA Status

0h = The I2CSDA signal is low.

1h = The I2CSDA signal is high.

0SCLR1h

I2C SCL Status

0h = The I2CSCL signal is low.

1h = The I2CSCL signal is high.

7.3.12 I2CMBLEN Register (Offset = 30h) [reset = 0h]

I2CMBLEN is shown in Figure 7-25 and described in Table 7-16.

Return to Summary Table.

This register contains the programmed length of bytes that are transferred during a burst request.

Figure 7-25 I2CMBLEN Register
313029282726252423222120191817161514131211109876543210
RESERVEDCNTL
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-16 I2CMBLEN Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0CNTLR/W0h

I2C Burst Length

This field contains the programmed length of bytes of the burst transaction. If BURST is enabled, this register must be set to a non-zero value, otherwise an error will occur.

7.3.13 I2CMBCNT Register (Offset = 34h) [reset = 0h]

I2CMBCNT is shown in Figure 7-26 and described in Table 7-17.

Return to Summary Table.

When BURST is active, the value in the I2CMBLEN register is copied into this register and decremented during the BURST transaction. This register can be used to determine the number of transfers that occurred when a BURST terminates early (as a result of a data NACK). When a BURST completes successfully, this register will contain 0.

Figure 7-26 I2CMBCNT Register
313029282726252423222120191817161514131211109876543210
RESERVEDCNTL
R-0hRo-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-17 I2CMBCNT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0CNTLRo0h

I2C Master Burst Count

This field contains the current count-down value of the BURST transaction.

7.3.14 I2CSOAR Register (Offset = 800h) [reset = 0h]

I2CSOAR is shown in Figure 7-27 and described in Table 7-18.

Return to Summary Table.

This register consists of seven address bits that identify the TM4E111BE6ZRB I2C device on the I2C bus.

Figure 7-27 I2CSOAR Register
313029282726252423222120191817161514131211109876543210
RESERVEDOAR
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-18 I2CSOAR Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0h
6-0OARR/W0h

I2C Slave Own Address

This field specifies bits A6 through A0 of the slave address.

7.3.15 I2CSCSR Register (Offset = 804h) [reset = 0h]

I2CSCSR is shown in Figure 7-28 and described in Table 7-19.

Return to Summary Table.

This register functions as a control register when written, and a status register when read.

Figure 7-28 I2CSCSR Register
3130292827262524
ACTDMARXACTDMATXRESERVED
R-0hR-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDQCMDRWQCMDSTOAR2SELFBR_OR_RXFIFOTREQ_OR_TXFIFORREQ_OR_DA
R-0hRC-0hRC-0hRO-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-19 I2CSCSR Register Field Descriptions
BitFieldTypeResetDescription
31ACTDMARXR0h

DMA RX Active Status

0h (R) = DMA RX is not active

1h (R) = DMA RX is active.

30ACTDMATXR0h

DMA RX Active Status

0h (R) = DMA RX is not active

1h (R) = DMA RX is active.

29-6RESERVEDR0h
5QCMDRWRC0h

Quick Command Read / Write

This bit only has meaning when the QCMDST bit is set.

0h (R) = Quick command was a write

1h (R) = Quick command was a read

4QCMDSTRC0h

Quick Command Status

0h (R) = The last transaction was a normal transaction or a transaction has not occurred.

1h (R) = The last transaction was a Quick Command transaction.

3OAR2SELRO0h

OAR2 Address Matched

This bit is reevaluated after every address comparison.

0h (R) = Either the address is not matched or the match is in legacy mode.

1h (R) = OAR2 address matched and ACKed by the slave.

2FBR_OR_RXFIFOR/W0h

First Byte Received (R) or RX FIFO Enable

This bit is only valid when the RREQ bit is set and is automatically cleared when data has been read from the I2CSDR register.

0h (W) = Disables RX FIFO

0h (R) = The first byte has not been received.

1h (W) = Enables RX FIFO

1h (R) = The first byte following the slave s own address has been received.

Note: This bit is not used for slave transmit operations.

1TREQ_OR_TXFIFOR/W0h

Transmit Request (R) or TX FIFO Enable (W)

0h (W) = Disables TX FIFO

0h (R) = No outstanding transmit request.

1h (W) = Enables TX FIFO

1h (R) = The I2C controller has been addressed as a slave transmitter and is using clock stretching to delay the master until data has been written to the I2CSDR register.

0RREQ_OR_DAR/W0h

Receive Request (R) or Device Active (W)

Once this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.

0h (W) = Disables the I2C slave operation.

0h (R) = No outstanding receive data.

1h (W) = Enables the I2C slave operation.

1h (R) = The I2C controller has outstanding receive data from the I2C master and is using clock stretching to delay the master until the data has been read from the I2CSDR register.

7.3.16 I2CSDR Register (Offset = 808h) [reset = 0h]

I2CSDR is shown in Figure 7-29 and described in Table 7-20.

Return to Summary Table.

Note:

This register is read-sensitive. See the register description for details.

This register contains the data to be transmitted when in the slave transmit state, and the data received when in the slave receive state. If the RXFIFO bit or TXFIFO bit are enabled in the I2CSCSR register, then this register is ignored and the data value being transferred from the FIFO is contained in the I2CFIFODATA register.

Note:

Best practice recommends that an application should not switch between the I2CSDR register and TX FIFO, or vice versa for successive transactions.

Figure 7-29 I2CSDR Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-20 I2CSDR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0DATAR/W0h

Data for Transfer

This field contains the data for transfer during a slave receive or transmit operation.

7.3.17 I2CSIMR Register (Offset = 80Ch) [reset = 0h]

I2CSIMR is shown in Figure 7-30 and described in Table 7-21.

Return to Summary Table.

This register controls whether a raw interrupt is promoted to a controller interrupt.

Figure 7-30 I2CSIMR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRXFFIM
R-0hR/W-0h
76543210
TXFEIMRXIMTXIMDMATXIMDMARXIMSTOPIMSTARTIMDATAIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-21 I2CSIMR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8RXFFIMR/W0h

Receive FIFO Full Interrupt Mask

0h = The RXFFRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The Receive FIFO Full interrupt is sent to the interrupt controller when the RXFFRIS bit in the I2CSRIS register is set.

7TXFEIMR/W0h

Transmit FIFO Empty Interrupt Mask

0h = The TXFERIS interrupt is suppressed and not sent to the interrupt controller.

1h = The Transmit FIFO Empty interrupt is sent to the interrupt controller when the TXFERIS bit in the I2CSRIS register is set.

6RXIMR/W0h

Receive FIFO Request Interrupt Mask

0h = The RXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The RX FIFO Request interrupt is sent to the interrupt controller when the RXRIS bit in the I2CSRIS register is set.

5TXIMR/W0h

Transmit FIFO Request Interrupt

0h = The TXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The TX FIFO Request interrupt is sent to the interrupt controller when the TXRIS bit in the I2CSRIS register is set.

4DMATXIMR/W0h

Transmit DMA Interrupt Mask

0h = The DMATXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The transmit DMA complete interrupt is sent to the interrupt controller when the DMATXRIS bit in the I2CSRIS register is set.

3DMARXIMR/W0h

Receive DMA Interrupt Mask

0h = The DMARXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The receive DMA complete interrupt is sent to the interrupt controller when the DMARXRIS bit in the I2CSRIS register is set.

2STOPIMR/W0h

Stop Condition Interrupt Mask

0h = The STOPRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The STOP condition interrupt is sent to the interrupt controller when the STOPRIS bit in the I2CSRIS register is set.

1STARTIMR/W0h

Start Condition Interrupt Mask

0h = The STARTRIS interrupt is suppressed and not sent to the interrupt controller.

1h = The START condition interrupt is sent to the interrupt controller when the STARTRIS bit in the I2CSRIS register is set.

0DATAIMR/W0h

Data Interrupt Mask

0h = The DATARIS interrupt is suppressed and not sent to the interrupt controller.

1h = Data interrupt sent to interrupt controller when DATARIS bit in the I2CSRIS register is set.

7.3.18 I2CSRIS Register (Offset = 810h) [reset = 0h]

I2CSRIS is shown in Figure 7-31 and described in Table 7-22.

Return to Summary Table.

This register specifies whether an interrupt is pending.

Figure 7-31 I2CSRIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRXFFRIS
R-0hR-0h
76543210
TXFERISRXRISTXRISDMATXRISDMARXRISSTOPRISSTARTRISDATARIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-22 I2CSRIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8RXFFRISR0h

Receive FIFO Full Raw Interrupt Status

This bit is cleared by writing a 1 to the RXFFIC bit in the I2CSICR register.

0h = No interrupt

1h = The Receive FIFO Full interrupt is pending.

7TXFERISR0h

Transmit FIFO Empty Raw Interrupt Status

This bit is cleared by writing a 1 to the TXFEIC bit in the I2CSICR register.

0h = No interrupt

1h = The Transmit FIFO Empty interrupt is pending.

Note that if the TXFERIS interrupt is cleared (by setting the TXFEIC bit) when the TX FIFO is empty, the TXFERIS interrupt does not reassert even though the TX FIFO remains empty in this situation.

6RXRISR0h

Receive FIFO Request Raw Interrupt Status

This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register.

0h = No interrupt

1h = The trigger value for the FIFO has been reached and a RX FIFO Request interrupt is pending.

5TXRISR0h

Receive FIFO Request Raw Interrupt Status

This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register.

0h = No interrupt

1h = The trigger value for the FIFO has been reached and a RX FIFO Request interrupt is pending.

4DMATXRISR0h

Transmit DMA Raw Interrupt Status

This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register.

0h = No interrupt

1h = A transmit DMA complete interrupt is pending.

3DMARXRISR0h

Receive DMA Raw Interrupt Status

This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR register.

0h = No interrupt

1h = A receive DMA complete interrupt is pending.

2STOPRISR0h

Stop Condition Raw Interrupt Status

This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register.

0h = No interrupt

1h = A STOP condition interrupt is pending.

1STARTRISR0h

Start Condition Raw Interrupt Status

This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register.

0h = No interrupt.

1h = A START condition interrupt is pending.

0DATARISR0h

Data Raw Interrupt Status

This interrupt encompasses the following:

  • slave transaction received
  • slave transaction requested
  • next byte transfer request

This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register.

0h = No interrupt.

1h = Slave Interrupt is pending.

7.3.19 I2CSMIS Register (Offset = 814h) [reset = 0h]

I2CSMIS is shown in Figure 7-32 and described in Table 7-23.

Return to Summary Table.

This register specifies whether an interrupt was signaled.

Figure 7-32 I2CSMIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRXFFMIS
R-0hR-0h
76543210
TXFEMISRXMISTXMISDMATXMISDMARXMISSTOPMISSTARTMISDATAMIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-23 I2CSMIS Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8RXFFMISR0h

Receive FIFO Full Interrupt Mask

This bit is cleared by writing a 1 to the RXFFIC bit in the I2CSICR register.

0h = No interrupt.

1h = An unmasked Receive FIFO Full interrupt was signaled and is pending.

7TXFEMISR0h

Transmit FIFO Empty Interrupt Mask

This bit is cleared by writing a 1 to the TXFEIC bit in the I2CSICR register.

0h = No interrupt.

1h = An unmasked Transmit FIFO Empty interrupt was signaled and is pending.

6RXMISR0h

Receive FIFO Request Interrupt Mask

This bit is cleared by writing a 1 to the RXIC bit in the I2CSICR register.

0h = No interrupt.

1h = An unmasked Receive FIFO Request interrupt was signaled and is pending.

5TXMISR0h

Transmit FIFO Request Interrupt Mask

This bit is cleared by writing a 1 to the TXIC bit in the I2CSICR register.

0h = No interrupt.

1h = An unmasked Transmit FIFO Request interrupt was signaled and is pending.

4DMATXMISR0h

Transmit DMA Masked Interrupt Status

This bit is cleared by writing a 1 to the DMATXIC bit in the I2CSICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked transmit DMA complete interrupt was signaled is pending.

3DMARXMISR0h

Receive DMA Masked Interrupt Status

This bit is cleared by writing a 1 to the DMARXIC bit in the I2CSICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked receive DMA complete interrupt was signaled is pending.

2STOPMISR0h

Stop Condition Masked Interrupt Status

This bit is cleared by writing a 1 to the STOPIC bit in the I2CSICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked STOP condition interrupt was signaled is pending.

1STARTMISR0h

Start Condition Masked Interrupt Status

This bit is cleared by writing a 1 to the STARTIC bit in the I2CSICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked START condition interrupt was signaled is pending.

0DATAMISR0h

Data Masked Interrupt Status

This bit is cleared by writing a 1 to the DATAIC bit in the I2CSICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked slave data interrupt was signaled is pending.

7.3.20 I2CSICR Register (Offset = 818h) [reset = 0h]

I2CSICR is shown in Figure 7-33 and described in Table 7-24.

Return to Summary Table.

This register clears the raw interrupt. A read of this register returns no meaningful data.

Figure 7-33 I2CSICR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRXFFIC
R-0hW-0h
76543210
TXFEICRXICTXICDMATXICDMARXICSTOPICSTARTICDATAIC
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-24 I2CSICR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8RXFFICW0h

Receive FIFO Full Interrupt Mask

Writing a 1 to this bit clears the RXFFIS bit in the I2CSRIS register and the RXFFMIS bit in the I2CSMIS register.

A read of this register returns no meaningful data.

7TXFEICW0h

Transmit FIFO Empty Interrupt Mask

Writing a 1 to this bit clears the TXFERIS bit in the I2CSRIS register and the TXFEMIS bit in the I2CSMIS register.

A read of this register returns no meaningful data.

6RXICW0h

Receive Request Interrupt Mask

Writing a 1 to this bit clears the RXRIS bit in the I2CSRIS register and the RXMIS bit in the I2CSMIS register.

A read of this register returns no meaningful data.

5TXICW0h

Transmit Request Interrupt Mask

Writing a 1 to this bit clears the TXRIS bit in the I2CSRIS register and the TXMIS bit in the I2CSMIS register.

A read of this register returns no meaningful data.

4DMATXICW0h

Transmit DMA Interrupt Clear

Writing a 1 to this bit clears the DMATXRIS bit in the I2CSRIS register and the DMATXMIS bit in the I2CSMIS register.

A read of this register returns no meaningful data.

3DMARXICW0h

Receive DMA Interrupt Clear

Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS register and the DMARXMIS bit in the I2CSMIS register.

A read of this register returns no meaningful data.

2STOPICW0h

Receive DMA Interrupt Clear

Writing a 1 to this bit clears the DMARXRIS bit in the I2CSRIS register and the DMARXMIS bit in the I2CSMIS register.

A read of this register returns no meaningful data.

1STARTICW0h

Start Condition Interrupt Clear

Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register and the STARTMIS bit in the I2CSMIS register.

A read of this register returns no meaningful data.

0DATAICW0h

Start Condition Interrupt Clear

Writing a 1 to this bit clears the STARTRIS bit in the I2CSRIS register and the STARTMIS bit in the I2CSMIS register.

A read of this register returns no meaningful data.

7.3.21 I2CSOAR2 Register (Offset = 81Ch) [reset = 0h]

I2CSOAR2 is shown in Figure 7-34 and described in Table 7-25.

Return to Summary Table.

This register consists of seven address bits that identify the alternate address for the I2C device on the I2C bus.

Figure 7-34 I2CSOAR2 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
OAR2ENOAR2
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-25 I2CSOAR2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7OAR2ENR/W0h

I2C Slave Own Address 2 Enable

0h = The alternate address is disabled.

1h = Enables the use of the alternate address in the OAR2 field.

6-0OAR2R/W0h

I2C Slave Own Address 2 This field specifies the alternate OAR2 address.

7.3.22 I2CSACKCTL Register (Offset = 820h) [reset = 0h]

I2CSACKCTL is shown in Figure 7-35 and described in Table 7-26.

Return to Summary Table.

This register enables the I2C slave to NACK for invalid data or command or ACK for valid data or command. The I2C clock is pulled low after the last data bit until this register is written.

Figure 7-35 I2CSACKCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDACKOVALACKOEN
R-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-26 I2CSACKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ACKOVALR/W0h

I2C Slave ACK Override Value

0h = An ACK is sent indicating valid data or command.

1h = A NACK is sent indicating invalid data or command.

0ACKOENR/W0h

I2C Slave ACK Override Enable

0h = A response in not provided.

1h = An ACK or NACK is sent according to the value written to the ACKOVAL bit.

7.3.23 I2CFIFODATA Register (Offset = F00h) [reset = 0h]

I2CFIFODATA is shown in Figure 7-36 and described in Table 7-27.

Return to Summary Table.

The I2C FIFO Data (I2CFIFODATA) register contains the current value of the top of the RX or TX FIFO stack being used in the a transfer.

Figure 7-36 I2CFIFODATA Register
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-27 I2CFIFODATA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0DATAR/W0h

I2C RX FIFO Data Byte

This field contains the current byte being read in the RX FIFO stack. This field contains the current byte written to the TX FIFO. For back to back transmit operations, the application should not switch between writing to the I2CSDR register and the I2CFIFODATA.

7.3.24 I2CFIFOCTL Register (Offset = F04h) [reset = 00040004h]

I2CFIFOCTL is shown in Figure 7-37 and described in Table 7-28.

Return to Summary Table.

The FIFO Control register can be programmed to control various aspects of the FIFO transaction, such as RX and TX FIFO assignment, byte count value for FIFO triggers, and flushing of the FIFOs.

Figure 7-37 I2CFIFOCTL Register
3130292827262524
RXASGNMTRXFLUSHDMARXENARESERVED
R/W-0hR/W-0hR/W-0hR-0h
2322212019181716
RESERVEDRXTRIG
R-0hR/W-4h
15141312111098
TXASGNMTTXFLUSHDMATXENARESERVED
R/W-0hR/W-0hR/W-0hR-0h
76543210
RESERVEDTXTRIG
R-0hR/W-4h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-28 I2CFIFOCTL Register Field Descriptions
BitFieldTypeResetDescription
31RXASGNMTR/W0h

RX Control Assignment

0h = RX FIFO is assigned to master

1h = RX FIFO is assigned to slave

30RXFLUSHR/W0h

RX FIFO Flush

Setting this bit flushes the RX FIFO. This bit self-clears when the flush has completed.

29DMARXENAR/W0h

DMA RX Channel Enable

0h = DMA RX channel disabled

1h = DMA RX channel enabled

28-19RESERVEDR0h
18-16RXTRIGR/W4h

RX FIFO Trigger

Indicates at what fill level the RX FIFO generates a trigger.

0h = Trigger when RX FIFO contains no bytes

1h = Trigger when Rx FIFO contains 1 or more bytes

2h = Trigger when Rx FIFO contains 2 or more bytes

3h = Trigger when Rx FIFO contains 3 or more bytes

4h = Trigger when Rx FIFO contains 4 or more bytes

5h = Trigger when Rx FIFO contains 5 or more bytes

6h = Trigger when Rx FIFO contains 6 or more bytes

7h = Trigger when Rx FIFO contains 7 or more bytes.

Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.

15TXASGNMTR/W0h

TX Control Assignment

0h = TX FIFO is assigned to Master

1h = TX FIFO is assigned to Slave

14TXFLUSHR/W0h

TX FIFO Flush

Setting this bit flushes the TX FIFO. This bit self-clears when the flush has completed.

13DMATXENAR/W0h

DMA TX Channel Enable

0h = DMA TX channel disabled

1h = DMA TX channel enabled

12-3RESERVEDR0h
2-0TXTRIGR/W4h

TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger is generated.

0h = Trigger when the TX FIFO is empty.

1h = Trigger when TX FIFO contains 1 byte

2h = Trigger when TX FIFO contains 2 bytes

3h = Trigger when TX FIFO 3 bytes

4h = Trigger when TX FIFO 4 bytes

5h = Trigger when TX FIFO 5 bytes

6h = Trigger when TX FIFO 6 bytes

7h = Trigger when TX FIFO 7 bytes

7.3.25 I2CFIFOSTATUS Register (Offset = F08h) [reset = 00010005h]

I2CFIFOSTATUS is shown in Figure 7-38 and described in Table 7-29.

Return to Summary Table.

This register contains the real-time status of the RX and TX FIFOs.

Figure 7-38 I2CFIFOSTATUS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRXABVTRIGRXFFRXFE
R-0hR-0hR-0hR-1h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTXBLWTRIGTXFFTXFE
R-0hR-1hR-0hR-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-29 I2CFIFOSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0h
18RXABVTRIGR0h

RX FIFO Above Trigger Level

0h = The number of bytes in RX FIFO is below the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register

1h = The number of bytes in the RX FIFO is above the trigger level programmed by the RXTRIG bit in the I2CFIFOCTL register

17RXFFR0h

RX FIFO Full

0h = The RX FIFO is not full.

1h = The RX FIFO is full.

16RXFER1h

RX FIFO Empty

0h = The RX FIFO is not empty.

1h = The RX FIFO is empty.

15-3RESERVEDR0h
2TXBLWTRIGR1h

TX FIFO Below Trigger Level

0h = The number of bytes in TX FIFO is above the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register

1h = The number of bytes in the TX FIFO is below the trigger level programmed by the TXTRIG bit in the I2CFIFOCTL register

1TXFFR0h

TX FIFO Full

0h = The TX FIFO is not full.

1h = The TX FIFO is full.

0TXFER1h

TX FIFO Empty

0h = The TX FIFO is not empty.

1h = The TX FIFO is empty.

7.3.26 I2CPP Register (Offset = FC0h) [reset = 1h]

I2CPP is shown in Figure 7-39 and described in Table 7-30.

Return to Summary Table.

The I2CPP register provides information regarding the properties of the I2C module.

Figure 7-39 I2CPP Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDHS
R-0hR-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-30 I2CPP Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0HSR1h

High-Speed Capable

0h = The interface is capable of standard or fast mode operation.

1h = Reserved

7.3.27 I2CPC Register (Offset = FC4h) [reset = 1h]

I2CPC is shown in Figure 7-40 and described in Table 7-31.

Return to Summary Table.

The I2CPC register allows software to enable features present in the I2C module.

Figure 7-40 I2CPC Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDHS
R-0hR-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-31 I2CPC Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0HSR1h

High-Speed Capable

0h = The interface is capable of standard or fast mode operation.

1h = Reserved. Must be set to 0