SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

12.5 I2S Registers

Control registers for the McASP are summarized in Table 12-3. The control registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 12-4. See the device-specific data manual for the memory address of these registers.

Control registers for the McASP Audio FIFO (AFIFO) are summarized in Table 12-5. The AFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control registers are accessed through the peripheral configuration port. See the device-specific data manual for the memory address of these registers.

Table 12-3 lists the memory-mapped registers for the I2S. All register offset addresses not listed in Table 12-3 should be considered as reserved locations and the register contents should not be modified.

Base address is 0x4401C000.

Table 12-3 I2S Registers Accessed Through Peripheral Configuration Port
OffsetAcronymRegister NameSection
14hPDIRPin DirectionSection 12.5.3
44hGBLCTLGlobal ControlSection 12.5.6
60hRGBLCTLReceiver Global Control. Alias of GBLCTL, only receive bits are affected - allows receiver to be reset independently from transmitterSection 12.5.7
64hRMASKReceive Format Unit Bit MaskSection 12.5.8
68hRFMTReceive Bit Stream FormatSection 12.5.9
6ChAFSRCTLReceive Frame Sync ControlSection 12.5.10
78hRTDMReceive TDM Time Slot 0-31Section 12.5.11
7ChRINTCTLReceiver Interrupt ControlSection 12.5.12
80hRSTATReceiver StatusSection 12.5.13
84hRSLOTCurrent Receive TDM Time SlotSection 12.5.14
8ChREVTCTLReceiver DMA Event ControlSection 12.5.15
A0hXGBLCTLTransmitter Global Control. Alias of GBLCTL, only transmit bits are affected - allows transmitter to be reset independently from receiverSection 12.5.16
A4hXMASKTransmit Format Unit Bit MaskSection 12.5.17
A8hXFMTTransmit Bit Stream FormatSection 12.5.18
AChAFSXCTLTransmit Frame Sync ControlSection 12.5.19
B0hACLKXCTLTransmit Clock ControlSection 12.5.20
B4hAHCLKXCTLTransmit High-frequency Clock ControlSection 12.5.21
B8hXTDMTransmit TDM Time Slot 0-31Section 12.5.22
BChXINTCTLTransmitter Interrupt ControlSection 12.5.23
C0hXSTATTransmitter StatusSection 12.5.24
C4hXSLOTCurrent Transmit TDM Time SlotSection 12.5.25
C8hXCLKCHKTransmit Clock Check Control
CChXEVTCTLTransmitter DMA Event ControlSection 12.5.26
180hSRCTL0Serializer Control Register 0Section 12.5.27
184hSRCTL1Serializer Control Register 1Section 12.5.27
200hXBUF0(1)Transmit Buffer Register for Serializer 0Section 12.5.28
204hXBUF1(1)Transmit Buffer Register for Serializer 1Section 12.5.28
280hRBUF0(2)Receive Buffer Register for Serializer 0Section 12.5.29
284hRBUF1(2)Receive Buffer Register for Serializer 1Section 12.5.29
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
Table 12-4 I2S Registers Accessed Through DMA Port
Hex AddressRegister NameRegister Description
Read AccessesRBUFReceive buffer DMA port address. Cycles through receive serializers, skipping over transmit serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Reads from DMA port only if XBUSEL = 0 in XFMT.
Write AccessesXBUFTransmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA port only if RBUSEL = 0 in RFMT.
Table 12-5 I2S AFIFO Registers Accessed Through Peripheral Configuration Port
OffsetAcronymRegisterSection
0hAFIFOREVAFIFO revision identification registerSection 12.5.1
10hWFIFOCTLWrite FIFO control registerSection 12.5.2
14hWFIFOSTSWrite FIFO status register
18hRFIFOCTLRead FIFO control registerSection 12.5.4
1ChRFIFOSTSRead FIFO status registerSection 12.5.5

12.5.1 AFIFOREV Register (Offset = 0h) [reset = 0h]

AFIFOREV is shown in Figure 12-4 and described in Table 12-6.

Return to Summary Table.

Figure 12-4 AFIFOREV Register
313029282726252423222120191817161514131211109876543210
REV
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-6 AFIFOREV Register Field Descriptions
BitFieldTypeResetDescription
31-0REVR0h

Identifies revision of peripheral.

12.5.2 WFIFOCTL Register (Offset = 10h) [reset = 1004h]

WFIFOCTL is shown in Figure 12-5 and described in Table 12-7.

Return to Summary Table.

The WNUMEVT and WNUMDMA values must be set before enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled before taking the I2S out of reset.

Figure 12-5 WFIFOCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDWENA
R-0hR/W-0h
15141312111098
WNUMEVT
R/W-10h
76543210
WNUMDMA
R/W-4h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-7 WFIFOCTL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

16WENAR/W0h

Write FIFO enable bit.

0h = Write FIFO is disabled. The WLVL bit in the Write FIFO status register (WFIFOSTS) is reset to 0 and pointers are initialized, that is, the Write FIFO is “flushed.”

1h = Write FIFO is enabled. If Write FIFO is to be enabled, it must be enabled before taking I2S out of reset.

15-8WNUMEVTR/W10h

Write word count per DMA event (32-bit). When the Write FIFO has space for at least WNUMEVT words of data, then an AXEVT (transmit DMA event) is generated to the host/DMA controller. This value should be set to a nonzero integer multiple of the number of serializers enabled as transmitters. This value must be set before enabling the Write FIFO.

0h = 0 words

1h = 1 word

2h = 2 words

3h - 40h = 3 to 16 words

41h - FFh = Reserved

7-0WNUMDMAR/W4h

Write word count per transfer (32-bit words). Upon a transmit DMA event from the McASP, WNUMDMA words are transferred from the Write FIFO to the I2S. This value must equal the number of McASP serializers used as transmitters. This value must be set before enabling the Write FIFO.

0h = 0 words

1h = 1 word

2h = 2 words

3h - 10h = 3 to 16 words

11h - FFh = Reserved

12.5.3 PDIR Register (Offset = 14h) [reset = 0h]

PDIR is shown in Figure 12-6 and described in Table 12-8.

Return to Summary Table.

The pin direction register (PDIR) specifies the direction of AXR[n], ACLKX, AHCLKX, AFSX, ACLKR, AHCLKR, and AFSR pins as either input or output pins.

Regardless of the pin function register (PFUNC) setting, each PDIR bit must be set to 1 for the specified pin to be enabled as an output, and each PDIR bit must be cleared to 0 for the specified pin to be an input.

For example, if the I2S is configured to use an internally-generated bit clock and the clock is to be driven out to the system, the PFUNC bit must be cleared to 0 (McASP function) and the PDIR bit must be set to 1 (an output).

When AXR[n] is configured to transmit, the PFUNC bit must be cleared to 0 (McASP function) and the PDIR bit must be set to 1 (an output). Similarly, when AXR[n] is configured to receive, the PFUNC bit must be cleared to 0 (McASP function) and the PDIR bit must be cleared to 0 (an input).

CAUTION:

Writing to Reserved Bits: Writing a value other than 0 to reserved bits in this register may cause improper device operation. This includes bits that are not implemented on a particular DSP.

Figure 12-6 PDIR Register
3130292827262524
AFSRAHCLKRACLKRAFSXAHCLKXACLKXAMUTERESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
AXR[15-0]
R/W-0h
76543210
AXR[15-0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-8 PDIR Register Field Descriptions
BitFieldTypeResetDescription
31AFSRR/W0h

Determines if AFSR pin functions as an input or output.

0h = Pin functions as input.

1h = Pin functions as output.

30AHCLKRR/W0h

Determines if AHCLKR pin functions as an input or output.

0h = Pin functions as input.

1h = Pin functions as output.

29ACLKRR/W0h

Determines if ACLKR pin functions as an input or output.

0h = Pin functions as input.

1h = Pin functions as output.

28AFSXR/W0h

Determines if AFSX pin functions as an input or output.

0h = Pin functions as input.

1h = Pin functions as output.

27AHCLKXR/W0h

Determines if AHCLKX pin functions as an input or output.

0h = Pin functions as input.

1h = Pin functions as output.

26ACLKXR/W0h

Determines if ACLKX pin functions as an input or output.

0h = Pin functions as input.

1h = Pin functions as output.

25AMUTER/W0h

Determines if AMUTE pin functions as an input or output.

0h = Pin functions as input.

1h = Pin functions as output.

24-16RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

15-0AXR[15-0]R/W0h

Determines if AXR[n] pin functions as an input or output.

0h = Pin functions as input.

1h = Pin functions as output.

12.5.4 RFIFOCTL Register (Offset = 18h) [reset = 1004h]

RFIFOCTL is shown in Figure 12-7 and described in Table 12-9.

Return to Summary Table.

The RNUMEVT and RNUMDMA values must be set before enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled before taking the McASP out of reset.

Figure 12-7 RFIFOCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRENA
R-0hR/W-0h
15141312111098
RNUMEVT
R/W-10h
76543210
RNUMDMA
R/W-4h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-9 RFIFOCTL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

16RENAR/W0h

Read FIFO enable bit.

0h = Read FIFO is disabled. The RLVL bit in the Read FIFO status register (RFIFOSTS) is reset to 0 and pointers are initialized, that is, the Read FIFO is “flushed.”

1h = Read FIFO is enabled. If Read FIFO is to be enabled, it must be enabled before taking McASP out of reset.

15-8RNUMEVTR/W10h

Read word count per DMA event (32-bit). When the Read FIFO has space for at least RNUMEVT words of data, then an AREVT (receive DMA event) is generated to the host/DMA controller. This value should be set to a nonzero integer multiple of the number of serializers enabled as receivers. This value must be set before enabling the Read FIFO.

0h = 0 words

1h = 1 word

2h = 2 words

3h - 40h = 3 to 16 words

41h - FFh = Reserved

7-0RNUMDMAR/W4h

Read word count per transfer (32-bit words). Upon a receive DMA event from the McASP, RNUMDMA words are transferred from the Read FIFO to the McASP. This value must equal the number of McASP serializers used as receivers. This value must be set before enabling the Read FIFO.

0h = 0 words

1h = 1 word

2h = 2 words

3h - 10h = 3 to 16 words

11h - FFh = Reserved

12.5.5 RFIFOSTS Register (Offset = 1Ch) [reset = 0h]

RFIFOSTS is shown in Figure 12-8 and described in Table 12-10.

Return to Summary Table.

Figure 12-8 RFIFOSTS Register
313029282726252423222120191817161514131211109876543210
RESERVEDRLVL
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-10 RFIFOSTS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

7-0RLVLR0h

Read level (read-only). Number of 32-bit words currently in the Read FIFO.

0h = 0 words currently in Read FIFO.

1h = 1 word currently in Read FIFO.

2h = 2 words currently in Read FIFO.

3h - 40h = 3 to 64 words currently in Read FIFO.

41h - FFh = Reserved

12.5.6 GBLCTL Register (Offset = 44h) [reset = 0h]

GBLCTL is shown in Figure 12-9 and described in Table 12-11.

Return to Summary Table.

The global control register (GBLCTL) provides initialization of the transmit and receive sections.

The bit fields in GBLCTL are synchronized and latched by the corresponding clocks (ACLKX for bits 12-8 and ACLKR for bits 4-0). Before GBLCTL is programmed, ensure that serial clocks are running. If the corresponding external serial clocks, ACLKX and ACLKR, are not yet running, select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL, and ACLKRCTL before GBLCTL is programmed. Also, after programming any bits in GBLCTL do not proceed until you have read back from GBLCTL and verified that the bits are latched in GBLCTL.

Figure 12-9 GBLCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDXFRSTXSMRSTXSRCLRXHCLKRSTXCLKRST
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRFRSTRSMRSTRSRCLRRHCLKRSTRCLKRST
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-11 GBLCTL Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

12XFRSTR/W0h

Transmit frame sync generator reset enable bit.

0h = Transmit frame sync generator is reset.

1h = Transmit frame sync generator is active. When released from reset, the transmit frame sync generator begins counting serial clocks and generating frame sync as programmed.

11XSMRSTR/W0h

Transmit state machine reset enable bit.

0h = Transmit state machine is held in reset. AXR[n] pin state: If PFUNC[n] = 0 and PDIR[n] = 1; then the serializer drives the AXR[n] pin to the state specified for inactive time slot (as determined by DISMOD bits in SRCTL).

1h = Transmit state machine is released from reset. When released from reset, the transmit state machine immediately transfers data from XRBUF[n] to XRSR[n]. The transmit state machine sets the underrun flag (XUNDRN) in XSTAT, if XRBUF[n] have not been preloaded with data before reset is released. The transmit state machine also immediately begins detecting frame sync and is ready to transmit. Transmit TDM time slot begins at slot 0 after reset is released.

10XSRCLRR/W0h

Transmit serializer clear enable bit. By clearing then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun will occur.

0h = Transmit serializers are cleared.

1h = Transmit serializers are active. When the transmit serializers are first taken out of reset (XSRCLR changes from 0 to 1), the transmit data ready bit (XDATA) in XSTAT is set to indicate XBUF is ready to be written.

9XHCLKRSTR/W0h

Transmit high-frequency clock divider reset enable bit.

0h = Transmit high-frequency clock divider is held in reset.

1h = Transmit high-frequency clock divider is running.

8XCLKRSTR/W0h

Transmit clock divider reset enable bit.

0h = Transmit clock divider is held in reset. When the clock divider is in reset, it passes through a divide-by-1 of its input.

1h = Transmit clock divider is running.

7-5RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

4RFRSTR/W0h

Receive frame sync generator reset enable bit.

0h = Receive frame sync generator is reset.

1h = Receive frame sync generator is active. When released from reset, the receive frame sync generator begins counting serial clocks and generating frame sync as programmed.

3RSMRSTR/W0h

Receive state machine reset enable bit.

0h = Receive state machine is held in reset.

1h = Receive state machine is released from reset. When released from reset, the receive state machine immediately begins detecting frame sync and is ready to receive. Receive TDM time slot begins at slot 0 after reset is released.

2RSRCLRR/W0h

Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed.

0h = Receive serializers are cleared.

1h = Receive serializers are active.

1RHCLKRSTR/W0h

Receive high-frequency clock divider reset enable bit.

0h = Receive high-frequency clock divider is held in reset.

1h = Receive high-frequency clock divider is running.

0RCLKRSTR/W0h

Receive high-frequency clock divider reset enable bit.

0h = Receive clock divider is held in reset. When the clock divider is in reset, it passes through a divide-by-1 of its input.

1h = Receive clock divider is running.

12.5.7 RGBLCTL Register (Offset = 60h) [reset = 0h]

RGBLCTL is shown in Figure 12-10 and described in Table 12-12.

Return to Summary Table.

Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL) affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL. RGBLCTL allows the receiver to be reset independently from the transmitter. See Section 3.8 for a detailed description of GBLCTL.

Figure 12-10 RGBLCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDXFRSTXSMRSTXSRCLRXHCLKRSTXCLKRST
R-0hR-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDRFRSTRSMRSTRSRCLRRHCLKRSTRCLKRST
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-12 RGBLCTL Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

12XFRSTR0h

Transmit frame sync generator reset enable bit. A read of this bit returns the XFRST bit value of GBLCTL. Writes have no effect.

11XSMRSTR0h

Transmit state machine reset enable bit. A read of this bit returns the XSMRST bit value of GBLCTL. Writes have no effect.

10XSRCLRR0h

Transmit serializer clear enable bit. A read of this bit returns the XSRCLR bit value of GBLCTL. Writes have no effect.

9XHCLKRSTR0h

Transmit high-frequency clock divider reset enable bit. A read of this bit returns the XHCLKRST bit value of GBLCTL. Writes have no effect.

8XCLKRSTR0h

Transmit clock divider reset enable bit. a read of this bit returns the XCLKRST bit value of GBLCTL. Writes have no effect.

7-5RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

4RFRSTR/W0h

Receive frame sync generator reset enable bit. A write to this bit affects the RFRST bit of GBLCTL.

0h = Receive frame sync generator is reset.

1h = Receive frame sync generator is active.

3RSMRSTR/W0h

Receive state machine reset enable bit. A write to this bit affects the RSMRST bit of GBLCTL.

0h = Receive state machine is held in reset.

1h = Receive state machine is released from reset.

2RSRCLRR/W0h

Receive serializer clear enable bit. A write to this bit affects the RSRCLR bit of GBLCTL.

0h = Receive serializers are cleared.

1h = Receive serializers are active.

1RHCLKRSTR/W0h

Receive high-frequency clock divider reset enable bit. A write to this bit affects the RHCLKRST bit of GBLCTL.

0h = Receive high-frequency clock divider is held in reset.

1h = Receive high-frequency clock divider is running.

0RCLKRSTR/W0h

Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL.

0h = Receive clock divider is held in reset.

1h = Receive clock divider is running.

12.5.8 RMASK Register (Offset = 64h) [reset = 0h]

RMASK is shown in Figure 12-11 and described in Table 12-13.

Return to Summary Table.

The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA.

Figure 12-11 RMASK Register
313029282726252423222120191817161514131211109876543210
RMASK[31-0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-13 RMASK Register Field Descriptions
BitFieldTypeResetDescription
31-0RMASK[31-0]R/W0h

Receive data mask enable bit.

0h = Corresponding bit of receive data (after passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (RPAD and RPBIT bits in RFMT).

1h = Corresponding bit of receive data (after passing through reverse and rotate units) is returned to CPU or DMA.

12.5.9 RFMT Register (Offset = 68h) [reset = 0h]

RFMT is shown in Figure 12-12 and described in Table 12-14.

Return to Summary Table.

The receive bit stream format register (RFMT) configures the receive data format.

Figure 12-12 RFMT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRDATDLY
R-0hR/W-0h
15141312111098
RRVRSRESERVEDRPBIT
R/W-0hR-0hR/W-0h
76543210
RSSZRBUSELRESERVED
R/W-0hR/W-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-14 RFMT Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

17-16RDATDLYR/W0h

Receive bit delay.

0h = Reserved

1h = 2-bit delay. The first receive data bit, AXR[n], occurs one ACLKR cycle after the receive frame sync (AFSR).

2h = Reserved

3h = Reserved

15RRVRSR/W0h

Receive serial bitstream order.

0h = Reserved

1h = Bitstream is MSB first. Bit reversal is performed in receive format bit reverse unit.

14-13RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

12-8RPBITR/W0h

RPBIT value determines which bit (as read by the CPU or DMA from RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h. 0h - 1Fh = Reserved

7-4RSSZR/W0h

Receive slot size. 0-2h = Reserved

3h = Slot size is 8 bits.

4h = Reserved

5h = Reserved

6h = Reserved

7h = Slot size is 16 bits.

8h = Reserved

9h = Reserved

Ah = Reserved

Bh = Slot size is 24 bits

Ch = Reserved

Dh = Reserved

Eh = Reserved

Fh = Reserved

3RBUSELR/W0h

Selects whether reads from serializer buffer XRBUF[n] originate from the peripheral configuration port or the DMA port.

0h = Reads from XRBUF[n] originate on DMA port. Reads from XRBUF[n] on the peripheral configuration port are ignored.

1h = Reads from XRBUF[n] originate on peripheral configuration port. Reads from XRBUF[n] on the DMA port are ignored.

2-0RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

12.5.10 AFSRCTL Register (Offset = 6Ch) [reset = 0h]

AFSRCTL is shown in Figure 12-13 and described in Table 12-15.

Return to Summary Table.

The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR).

Figure 12-13 AFSRCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RMOD
R/W-0h
76543210
RMODRESERVEDFRWIDRESERVEDFSRMFSRP
R/W-0hR-0hR/W-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-15 AFSRCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

15-7RMODR/W0h

Receive frame sync mode select bits.

0h = Reserved

1h = Reserved

2h = 2-slot TDM (I2S mode)

6-5RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

4FRWIDR/W0h

Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period.

0h = Reserved

1h = Single word

3-2RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

1FSRMR/W0h

Receive frame sync generation select bit.

0h = Externally-generated receive frame sync

1h = Internally-generated receive frame sync

0FSRPR/W0h

Receive frame sync polarity select bit.

0h = Reserved

1h = A falling edge on receive frame sync (AFSR) indicates the beginning of a frame.

12.5.11 RTDM Register (Offset = 78h) [reset = 0h]

RTDM is shown in Figure 12-14 and described in Table 12-16.

Return to Summary Table.

The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active.

Figure 12-14 RTDM Register
3130292827262524
RESERVED
R/W-0h
2322212019181716
RESERVED
R/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDRTDMS1RTDMS0
R/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-16 RTDM Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

1RTDMS1R/W0h

Receiver mode enable for TDM slot 1.

0h = Receive TDM time slot 1 is inactive. The receive serializer does not shift in data during this slot.

1h = Receive TDM time slot 1 is active. The receive serializer shifts in data during this slot.

0RTDMS0R/W0h

Receiver mode enable for TDM slot 0.

0h = Receive TDM time slot 0 is inactive. The receive serializer does not shift in data during this slot.

1h = Receive TDM time slot 0 is active. The receive serializer shifts in data during this slot.

12.5.12 RINTCTL Register (Offset = 7Ch) [reset = 0h]

RINTCTL is shown in Figure 12-15 and described in Table 12-17.

Return to Summary Table.

The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates RINT. See Section 12.5.23 for a description of the interrupt conditions.

Figure 12-15 RINTCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RSTAFRMRESERVEDRDATARLASTRESERVEDRSYNCERRROVRN
R/W-0hR-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-17 RINTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

7RSTAFRMR/W0h

Receive start of frame interrupt enable bit.

0h = Interrupt is disabled. A receive start of frame interrupt does not generate a McASP receive interrupt (RINT).

1h = Interrupt is enabled. A receive start of frame interrupt generates a McASP receive interrupt (RINT).

6RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

5RDATAR/W0h

Receive data ready interrupt enable bit.

0h = Interrupt is disabled. A receive data ready interrupt does not generate a McASP receive interrupt (RINT).

1h = Interrupt is enabled. A receive data ready interrupt generates a McASP receive interrupt (RINT).

4RLASTR/W0h

Receive last slot interrupt enable bit. 0h = Interrupt is disabled. A receive last slot interrupt does not generate a McASP receive interrupt (RINT). 1h = Interrupt is enabled. A receive last slot interrupt generates a McASP receive interrupt (RINT).

3-2RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

1RSYNCERRR/W0h

Unexpected receive frame sync interrupt enable bit.

0h = Interrupt is disabled. An unexpected receive frame sync interrupt does not generate a McASP receive interrupt (RINT).

1h = Interrupt is enabled. An unexpected receive frame sync interrupt generates a McASP receive interrupt (RINT).

0ROVRNR/W0h

Receiver overrun interrupt enable bit.

0h = Interrupt is disabled. A receiver overrun interrupt does not generate a McASP receive interrupt (RINT).

1h = Interrupt is enabled. A receiver overrun interrupt generates a McASP receive interrupt (RINT).

12.5.13 RSTAT Register (Offset = 80h) [reset = 0h]

RSTAT is shown in Figure 12-16 and described in Table 12-18.

Return to Summary Table.

The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set. This also causes a new interrupt request to be generated.

Figure 12-16 RSTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRERR
R-0hR/W-0h
76543210
RDMAERRRSTAFRMRDATARLASTRTDMSLOTRESERVEDRSYNCERRROVRN
R/W-0hR/W-0hR/W-0hR/W-0hR-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-18 RSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

8RERRR/W0h

RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error interrupt has occurred.

0h = No errors have occurred.

1h = An error has occurred.

7RDMAERRR/W0h

Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the DMA port in a given time slot than were programmed as receivers. Causes a receive interrupt (RINT), if this bit is set and RDMAERR in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.

0h = Receive DMA error did not occur.

1h = Receive DMA error did occur.

6RSTAFRMR/W0h

Receive start of frame flag. Causes a receive interrupt (RINT), if this bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.

0h = No new receive frame sync (AFSR) is detected.

1h = A new receive frame sync (AFSR) is detected.

5RDATAR/W0h

Receive data ready flag. Causes a receive interrupt (RINT), if this bit is set and RDATA in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.

0h = No new data in RBUF.

1h = Data is transferred from XRSR to RBUF and ready to be serviced by the CPU or DMA. When RDATA is set, it always causes a DMA event (AREVT).

4RLASTR/W0h

Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. Causes a receive interrupt (RINT), if this bit is set and RLAST in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.

0h = Current slot is not the last slot in a frame.

1h = Current slot is the last slot in a frame. RDATA is also set.

3RTDMSLOTR0h

Returns the LSB of RSLOT. Allows a single read of RSTAT to determine whether the current TDM time slot is even or odd.

0h = Current TDM time slot is odd.

1h = Current TDM time slot is even.

2RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

1RSYNCERRR/W0h

Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs before it is expected. Causes a receive interrupt (RINT), if this bit is set and RSYNCERR in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.

0h = Unexpected receive frame sync did not occur.

1h = Unexpected receive frame sync did occur.

0ROVRNR/W0h

Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. Causes a receive interrupt (RINT), if this bit is set and ROVRN in RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect.

0h = Receiver overrun did not occur.

1h = Receiver overrun did occur.

12.5.14 RSLOT Register (Offset = 84h) [reset = 0h]

RSLOT is shown in Figure 12-17 and described in Table 12-19.

Return to Summary Table.

The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame.

Figure 12-17 RSLOT Register
313029282726252423222120191817161514131211109876543210
RESERVEDRSLOTCNT
R-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-19 RSLOT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

8-0RSLOTCNTR0h

Current receive time slot count. Legal values: 0 or 1

12.5.15 REVTCTL Register (Offset = 8Ch) [reset = 0h]

REVTCTL is shown in Figure 12-18 and described in Table 12-20.

Return to Summary Table.

CAUTION:

Accessing REVTCTL when not implemented on a specific DSP may cause improper device operation.

Figure 12-18 REVTCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRDATDMA
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-20 REVTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

0RDATDMAR/W0h

Receive data DMA request enable bit. If writing to this field, always write the default value of 0.

0h = Receive data DMA request is enabled.

1h = Reserved.

12.5.16 XGBLCTL Register (Offset = A0h) [reset = 0h]

XGBLCTL is shown in Figure 12-19 and described in Table 12-21.

Return to Summary Table.

Alias of the global control register (GBLCTL). Writing to the transmitter global control register (XGBLCTL) affects only the transmit bits of GBLCTL (bits 12-8). Reads from XGBLCTL return the value of GBLCTL. XGBLCTL allows the transmitter to be reset independently from the receiver.

Figure 12-19 XGBLCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDXFRSTXSMRSTXSRCLRXHCLKRSTXCLKRST
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDRFRSTRSMRSTRSRCLRRHCLKRSTRCLKRST
R-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-21 XGBLCTL Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

12XFRSTR/W0h

Transmit frame sync generator reset enable bit. A write to this bit affects the XFRST bit of GBLCTL.

0h = Transmit frame sync generator is reset.

1h = Transmit frame sync generator is active.

11XSMRSTR/W0h

Transmit state machine reset enable bit. A write to this bit affects the XSMRST bit of GBLCTL.

0h = Transmit state machine is held in reset.

1h = Transmit state machine is released from reset.

10XSRCLRR/W0h

Transmit serializer clear enable bit. A write to this bit affects the XSRCLR bit of GBLCTL.

0h = Transmit serializers are cleared.

1h = Transmit serializers are active.

9XHCLKRSTR/W0h

Transmit high-frequency clock divider reset enable bit. A write to this bit affects the XHCLKRST bit of GBLCTL.

0h = Transmit high-frequency clock divider is held in reset.

1h = Transmit high-frequency clock divider is running.

8XCLKRSTR/W0h

Transmit clock divider reset enable bit. A write to this bit affects the XCLKRST bit of GBLCTL.

0h = Transmit clock divider is held in reset.

1h = Transmit clock divider is running.

7-5RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

4RFRSTR0h

Receive frame sync generator reset enable bit. A read of this bit returns the RFRST bit value of GBLCTL. Writes have no effect.

3RSMRSTR0h

Receive state machine reset enable bit. A read of this bit returns the RSMRST bit value of GBLCTL. Writes have no effect.

2RSRCLRR0h

Receive serializer clear enable bit. A read of this bit returns the RSRSCLR bit value of GBLCTL. Writes have no effect.

1RHCLKRSTR0h

Receive high-frequency clock divider reset enable bit. A read of this bit returns the RHCLKRST bit value of GBLCTL. Writes have no effect.

0RCLKRSTR0h

Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect.

12.5.17 XMASK Register (Offset = A4h) [reset = 0h]

XMASK is shown in Figure 12-20 and described in Table 12-22.

Return to Summary Table.

The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP.

Figure 12-20 XMASK Register
313029282726252423222120191817161514131211109876543210
XMASK[31-0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-22 XMASK Register Field Descriptions
BitFieldTypeResetDescription
31-0XMASK[31-0]R/W0h

Transmit data mask enable bit.

0h = Corresponding bit of transmit data (before passing through reverse and rotate units) is masked out and then padded with the selected bit pad value (XPAD and XPBIT bits in XFMT), which is transmitted out the McASP in place of the original bit.

1h = Corresponding bit of transmit data (before passing through reverse and rotate units) is transmitted out the McASP.

12.5.18 XFMT Register (Offset = A8h) [reset = 0h]

XFMT is shown in Figure 12-21 and described in Table 12-23.

Return to Summary Table.

The transmit bit stream format register (XFMT) configures the transmit data format.

Figure 12-21 XFMT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDXDATDLY
R-0hR/W-0h
15141312111098
XRVRSRESERVED
R/W-0hR-0h
76543210
XSSZXBUSELXROT
R/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-23 XFMT Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

17-16XDATDLYR/W0h

Transmit sync bit delay.

15XRVRSR/W0h

Transmit serial bitstream order.

0h = Reserved

1h = Bitstream is MSB first. Bit reversal is performed in receive format bit reverse unit.

14-8RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

7-4XSSZR/W0h

Transmit slot size. 0-2h = Reserved

3h = Slot size is 8 bits.

4h = Reserved

5h = Reserved

6h = Reserved

7h = Slot size is 16 bits.

8h = Reserved

9h = Reserved

Ah = Reserved

Bh = Slot size is 24 bits

Ch = Reserved

Dh = Reserved

Eh = Reserved

Fh = Reserved

3XBUSELR/W0h

Selects whether writes to serializer buffer XRBUF[n] originate from the peripheral configuration port or the DMA port.

0h = Writes to XRBUF[n] originate on DMA port. Writes to XRBUF[n] on the peripheral configuration port are ignored with no effect to the McASP.

1h = Writes to XRBUF[n] originate on peripheral configuration port. Writes to XRBUF[n] on the DMA port are ignored with no effect to the McASP.

2-0XROTR/W0h

Right-rotation value for transmit rotate right format unit.

0h = Reserved

1h = Reserved

2h = Rotate right by 8 bit positions.

3h = Reserved

4h = Rotate right by 16 bit positions.

5h = Reserved

6h = Rotate right by 24 bit positions.

7h = Reserved

12.5.19 AFSXCTL Register (Offset = ACh) [reset = 0h]

AFSXCTL is shown in Figure 12-22 and described in Table 12-24.

Return to Summary Table.

The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX).

Figure 12-22 AFSXCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
XMOD
R/W-0h
76543210
XMODRESERVEDFXWIDRESERVEDFSXMFSXP
R/W-0hR-0hR/W-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-24 AFSXCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

15-7XMODR/W0h

Transmit frame sync mode select bits.

0h = Reserved

1h = Reserved

2h-20h = 2-slot TDM (I2S mode)

180h - 1FFh = Reserved

6-5RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

4FXWIDR/W0h

Transmit frame sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period.

0h = Reserved

1h = Single word

3-2RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

1FSXMR/W0h

Transmit frame sync generation select bit.

0h = Externally-generated transmit frame sync

1h = Internally-generated transmit frame sync

0FSXPR/W0h

Transmit frame sync polarity select bit.

0h = Reserved

1h = A falling edge on transmit frame sync (AFSX) indicates the beginning of a frame.

12.5.20 ACLKXCTL Register (Offset = B0h) [reset = 60h]

ACLKXCTL is shown in Figure 12-23 and described in Table 12-25.

Return to Summary Table.

The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator.

Figure 12-23 ACLKXCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CLKXPASYNCCLKXMCLKXDIV
R/W-0hR/W-1hR/W-1hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-25 ACLKXCTL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

7CLKXPR/W0h

Transmit bitstream clock polarity select bit.

0h = Reserved

1h = Falling edge. External receiver samples data on the rising edge of the serial clock, so the transmitter must shift data out on the falling edge of the serial clock.

6ASYNCR/W1h

Transmit/receive operation asynchronous enable bit.

0h = Synchronous. Transmit clock and frame sync provides the source for both the transmit and receive sections. Note that in this mode, the receive bit clock is an inverted version of the transmit bit clock.

1h = Reserved

5CLKXMR/W1h

Transmit bit clock source bit.

0h = External transmit clock source from ACLKX pin.

1h = Internal transmit clock source from output of programmable bit clock divider.

4-0CLKXDIVR/W0h

Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX.

0h = Divide-by-1

1h = Divide-by-2

2h - 1Fh = Divide-by-3 to divide-by-32

12.5.21 AHCLKXCTL Register (Offset = B4h) [reset = 8000h]

AHCLKXCTL is shown in Figure 12-24 and described in Table 12-26.

Return to Summary Table.

The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator.

Figure 12-24 AHCLKXCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
HCLKXMRESERVEDHCLKXDIV
R/W-1hR-0hR/W-0h
76543210
HCLKXDIV
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-26 AHCLKXCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

15HCLKXMR/W1h

Transmit high-frequency clock source bit.

0h = Reserved

1h = Internal transmit high-frequency clock source from output of programmable high clock divider.

14-12RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

11-0HCLKXDIVR/W0h

Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX.

0h = Divide-by-1

1h = Divide-by-2

2h - FFFh = Divide-by-3 to divide-by-4096

12.5.22 XTDM Register (Offset = B8h) [reset = 0h]

XTDM is shown in Figure 12-25 and described in Table 12-27.

Return to Summary Table.

The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active. TDM time slot counter range is extended to 384 slots (to support SPDIF blocks of 384 subframes). XTDM operates modulo 32, that is, XTDMS specifies the TDM activity for time slots 0, 32, 64, 96, 128, and so forth.

Figure 12-25 XTDM Register
313029282726252423222120191817161514131211109876543210
XTDMS[31-0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-27 XTDM Register Field Descriptions
BitFieldTypeResetDescription
31-0XTDMS[31-0]R/W0h

Transmitter mode during TDM time slot n.

0h = Transmit TDM time slot n is inactive. The transmit serializer does not shift out data during this slot.

1h = Transmit TDM time slot n is active. The transmit serializer shifts out data during this slot according to the serializer control register (SRCTL).

12.5.23 XINTCTL Register (Offset = BCh) [reset = 0h]

XINTCTL is shown in Figure 12-26 and described in Table 12-28.

Return to Summary Table.

The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP conditions generates XINT.

Figure 12-26 XINTCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
XSTAFRMRESERVEDXDATAXLASTRESERVEDXSYNCERRXUNDRN
R/W-0hR-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-28 XINTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

7XSTAFRMR/W0h

Transmit start of frame interrupt enable bit.

0h = Interrupt is disabled. A transmit start of frame interrupt does not generate a McASP transmit interrupt (XINT).

1h = Interrupt is enabled. A transmit start of frame interrupt generates a McASP transmit interrupt (XINT).

6RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

5XDATAR/W0h

Transmit data ready interrupt enable bit.

0h = Interrupt is disabled. A transmit data ready interrupt does not generate a McASP transmit interrupt (XINT).

1h = Interrupt is enabled. A transmit data ready interrupt generates a McASP transmit interrupt (XINT).

4XLASTR/W0h

Transmit last slot interrupt enable bit.

0h = Interrupt is disabled. A transmit last slot interrupt does not generate a McASP transmit interrupt (XINT).

1h = Interrupt is enabled. A transmit last slot interrupt generates a McASP transmit interrupt (XINT).

3-2RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

1XSYNCERRR/W0h

Unexpected transmit frame sync interrupt enable bit.

0h = Interrupt is disabled. An unexpected transmit frame sync interrupt does not generate a McASP transmit interrupt (XINT).

1h = Interrupt is enabled. An unexpected transmit frame sync interrupt generates a McASP transmit interrupt (XINT).

0XUNDRNR/W0h

Transmitter underrun interrupt enable bit.

0h = Interrupt is disabled. A transmitter underrun interrupt does not generate a McASP transmit interrupt (XINT).

1h = Interrupt is enabled. A transmitter underrun interrupt generates a McASP transmit interrupt (XINT).

12.5.24 XSTAT Register (Offset = C0h) [reset = 0h]

XSTAT is shown in Figure 12-27 and described in Table 12-29.

Return to Summary Table.

The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number. If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set. This also causes a new interrupt request to be generated.

Figure 12-27 XSTAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDXERR
R-0hR/W-0h
76543210
RESERVEDXSTAFRMXDATAXLASTXTDMSLOTRESERVEDXSYNCERRXUNDRN
R-0hR/W-0hR/W-0hR/W-0hR-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-29 XSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

8XERRR/W0h

XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR Allows a single bit to be checked to determine if a transmitter error interrupt has occurred.

0h = No errors have occurred.

1h = An error has occurred.

7RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

6XSTAFRMR/W0h

Transmit start of frame flag. Causes a transmit interrupt (XINT), if this bit is set and XSTAFRM in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect.

0h = No new transmit frame sync (AFSX) is detected.

1h = A new transmit frame sync (AFSX) is detected.

5XDATAR/W0h

Transmit data ready flag. Causes a transmit interrupt (XINT), if this bit is set and XDATA in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect.

0h = XBUF is written and is full.

1h = Data is copied from XBUF to XRSR. XBUF is empty and ready to be written. XDATA is also set when the transmit serializers are taken out of reset. When XDATA is set, it always causes a DMA event (AXEVT).

4XLASTR/W0h

Transmit last slot flag. XLAST is set along with XDATA, if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT), if this bit is set and XLAST in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect.

0h = Current slot is not the last slot in a frame.

1h = Current slot is the last slot in a frame. XDATA is also set.

3XTDMSLOTR0h

Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd.

0h = Current TDM time slot is odd.

1h = Current TDM time slot is even.

2RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

1XSYNCERRR/W0h

Unexpected transmit frame sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT), if this bit is set and XSYNCERR in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect.

0h = Unexpected transmit frame sync did not occur.

1h = Unexpected transmit frame sync did occur.

0XUNDRNR/W0h

Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF to XRSR, but XBUF has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT), if this bit is set and XUNDRN in XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect.

0h = Transmitter underrun did not occur.

1h = Transmitter underrun did occur.

12.5.25 XSLOT Register (Offset = C4h) [reset = 17Fh]

XSLOT is shown in Figure 12-28 and described in Table 12-30.

Return to Summary Table.

The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame.

Figure 12-28 XSLOT Register
313029282726252423222120191817161514131211109876543210
RESERVEDXSLOTCNT
R-0hR-17Fh
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-30 XSLOT Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

8-0XSLOTCNTR17Fh

Current transmit time slot count. Legal values: 0 to 1

12.5.26 XEVTCTL Register (Offset = CCh) [reset = 0h]

XEVTCTL is shown in Figure 12-29 and described in Table 12-31.

Return to Summary Table.

CAUTION:

Accessing XEVTCTL when not implemented on a specific DSP may cause improper device operation.

Figure 12-29 XEVTCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDXDATDMA
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-31 XEVTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

0XDATDMAR/W0h

Transmit data DMA request enable bit. If writing to this field, always write the default value of 0.

0h = Transmit data DMA request is enabled.

1h = Reserved.

12.5.27 SRCTLn Register (Offset = 180h) [reset = 0h]

SRCTLn is shown in Figure 12-30 and described in Table 12-32.

Return to Summary Table.

Each serializer on the McASP has a serializer control register (SRCTL). There are up to 16 serializers per McASP.

CAUTION:

Accessing SRCTLn when not implemented on a specific DSP may cause improper device operation.

Figure 12-30 SRCTLn Registers
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRRDYXRDYDISMODSRMOD
R-0hR-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-32 SRCTLn Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved. The reserved bit location always returns the default value. A value written to this field has no effect. If writing to this field, always write the default value for future device compatibility.

5RRDYR0h

Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSR to RBUF.

0h = Receive buffer (RBUF) is empty.

1h = Receive buffer (RBUF) contains data and must be read before the start of the next time slot or a receiver overrun occurs.

4XRDYR0h

Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0).

0h = Transmit buffer (XBUF) contains data.

1h = Transmit buffer (XBUF) is empty and must be written before the start of the next time slot or a transmit underrun occurs.

3-2DISMODR/W0h

Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0).

0h = Drive on pin is 3-state.

1h = Reserved

2h = Drive on pin is logic low.

3h = Drive on pin is logic high.

1-0SRMODR/W0h

Serializer mode bit.

0h = Serializer is inactive.

1h = Serializer is transmitter.

2h = Serializer is receiver.

3h = Reserved

12.5.28 XBUFn Register (Offset = 200h) [reset = 0h]

XBUFn is shown in Figure 12-31 and described in Table 12-33.

Return to Summary Table.

The transmit buffers for the serializers (XBUF) hold data from the transmit format unit.

CAUTION:

Accessing XBUF registers that are not implemented on a specific DSP may cause improper device operation.

Figure 12-31 XBUFn Registers
313029282726252423222120191817161514131211109876543210
XBUFn
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-33 XBUFn Register Field Descriptions
BitFieldTypeResetDescription
31-0XBUFnR/W0h

For transmit operations, the XBUF is an alias of the XRBUF in the serializer. The XBUF can be accessed through the peripheral configuration port (see ) or through the DMA port (see ).

12.5.29 RBUFn Register (Offset = 280h) [reset = 0h]

RBUFn is shown in Figure 12-32 and described in Table 12-34.

Return to Summary Table.

The receive buffers for the serializers (RBUF) hold data from the serializer before the data goes to the receive format unit.

CAUTION:

Accessing RBUF registers that are not implemented on a specific DSP may cause improper device operation.

Figure 12-32 RBUFn Registers
313029282726252423222120191817161514131211109876543210
RBUFn
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-34 RBUFn Register Field Descriptions
BitFieldTypeResetDescription
31-0RBUFnR/W0h

For receive operations, the RBUF is an alias of the XRBUF in the serializer. The RBUF can be accessed through the peripheral configuration port (see ) or through the DMA port (see ).