SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

9.5 Timer Registers

Table 9-8 lists the memory-mapped Timer registers. All register offset addresses not listed in Table 9-8 should be considered as reserved locations, and the register contents should not be modified.

Table 9-8 Timer Registers
OffsetAcronymRegister NameSection
0hGPTMCFGGPTM ConfigurationSection 9.5.1
4hGPTMTAMRGPTM Timer A ModeSection 9.5.2
8hGPTMTBMRGPTM Timer B ModeSection 9.5.3
ChGPTMCTLGPTM ControlSection 9.5.4
18hGPTMIMRGPTM Interrupt MaskSection 9.5.5
1ChGPTMRISGPTM Raw Interrupt StatusSection 9.5.6
20hGPTMMISGPTM Masked Interrupt StatusSection 9.5.7
24hGPTMICRGPTM Interrupt ClearSection 9.5.8
28hGPTMTAILRGPTM Timer A Interval LoadSection 9.5.9
2ChGPTMTBILRGPTM Timer B Interval LoadSection 9.5.10
30hGPTMTAMATCHRGPTM Timer A MatchSection 9.5.11
34hGPTMTBMATCHRGPTM Timer B MatchSection 9.5.12
38hGPTMTAPRGPTM Timer A PrescaleSection 9.5.13
3ChGPTMTBPRGPTM Timer B PrescaleSection 9.5.14
40hGPTMTAPMRGPTM Timer A Prescale MatchSection 9.5.15
44hGPTMTBPMRGPTM Timer B Prescale MatchSection 9.5.16
48hGPTMTARGPTM Timer ASection 9.5.17
4ChGPTMTBRGPTM Timer BSection 9.5.18
50hGPTMTAVGPTM Timer A ValueSection 9.5.19
54hGPTMTBVGPTM Timer B ValueSection 9.5.20
6ChGPTMDMAEVGPTM DMA EventSection 9.5.21

9.5.1 GPTMCFG Register (offset = 0h) [reset = 0h]

GPTMCFG is shown in Figure 9-5 and described in Table 9-9.

This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode.

Note:

Bits in this register should only be changed when the TAEN and TBEN bits in the GPTMCTL register are cleared.

Figure 9-5 GPTMCFG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDGPTMCFG
R-0hR/W-0h
Table 9-9 GPTMCFG Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2-0GPTMCFGR/W0h

GPTM Configuration The GPTMCFG values are defined as follows:

0h = For a 16/32-bit timer, this value selects the 32-bit timer configuration.

1h-3h = Reserved

4h = For a 16/32-bit timer, this value selects the 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR.

5h - 7h = Reserved

9.5.2 GPTMTAMR Register (offset = 4h) [reset = 0h]

GPTMTAMR is shown in Figure 9-6 and described in Table 9-10.

This register configures the GPTM, based on the configuration selected in the GPTMCFG register. When in PWM mode, set the TAAMS bit, clear the TACMR bit, and configure the TAMR field to 0x1 or 0x2.

Figure 9-6 GPTMTAMR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTAPLOTAMRSUTAPWMIETAILD
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDTAMIETACDIRTAAMSTACMIRTAMR
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-10 GPTMTAMR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11TAPLOR/W0h

GPTM Timer A PWM Legacy Operation

0h = Legacy operation with CCP pin driven Low when the GPTMTAILR is reloaded after the timer reaches 0.

1h = CCP is driven High when the GPTMTAILR is reloaded after the timer reaches 0.

10TAMRSUR/W0h

GPTM Timer A Match Register Update. If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAMATCHR and GPTMTAPR are updated when the timer is enabled. If the timer is stalled (TASTALL is set), GPTMTAMATCHR and GPTMTAPR are updated according to the configuration of this bit.

0h = Update the GPTMTAMATCHR register and the GPTMTAPR register, if used, on the next cycle.

1h = Update the GPTMTAMATCHR register and the GPTMTAPR register, if used, on the next time-out.

9TAPWMIER/W0h

GPTM Timer A PWM Interrupt Enable. This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output, as defined by the TAEVENT field in the GPTMCTL register. In addition, when this bit is set and a capture event occurs, Timer A automatically generates triggers to the DMA if the trigger capability is enabled, by setting the TAOTE bit in the GPTMCTL register and the CAEDMAEN bit in the GPTMDMAEV register, respectively. This bit is only valid in PWM mode.

0h = Capture event interrupt is disabled.

1h = Capture event interrupt is enabled.

8TAILDR/W0h

GPTM Timer A Interval Load Write. Note the state of this bit has no effect when counting up. The bit descriptions above apply if the timer is enabled and running. If the timer is disabled (TAEN is clear) when this bit is set, GPTMTAR, GPTMTAV, and GPTMTAPs are updated when the timer is enabled. If the timer is stalled (TASTALL is set), GPTMTAR and GPTMTAPS are updated according to the configuration of this bit.

0h = Updates the GPTMTAR and GPTMTAV registers with the value in the GPTMTAILR register on the next cycle. Also updates the GPTMTAPS register with the value in the GPTMTAPR register on the next cycle.

1h = Updates the GPTMTAR and GPTMTAV registers with the value in the GPTMTAILR register on the next time-out. Also updates the GPTMTAPS register with the value in the GPTMTAPR register on the next time-out.

7-6RESERVEDR0h
5TAMIER/W0h

GPTM Timer A Match Interrupt Enable

0h = The match interrupt is disabled for match events. Additionally, triggers to the DMA on match events are prevented.

1h = An interrupt is generated when the match value in the GPTMTAMATCHR register is reached in the one-shot and periodic modes.

4TACDIRR/W0h

GPTM Timer A Count Direction. When in PWM mode, the status of this bit is ignored. PWM mode always counts down.

0h = The timer counts down.

1h = The timer counts up. When counting up, the timer starts from a value of 0x0.

3TAAMSR/W0h

GPTM Timer A Alternate Mode Select. The TAAMS values are defined as follows. Note: To enable PWM mode, clear the TACMR bit and configure the TAMR field to 0x1 or 0x2.

0h = Capture or compare mode is enabled.

1h = PWM mode is enabled.

2TACMIRR/W0h

GPTM Timer A Capture Mode. The TACMR values are defined as follows:

0h = Edge-count mode

1h = Edge-time mode

1-0TAMRR/W0h

GPTM Timer A Mode. The TAMR values are defined as follows: The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register.

0h = Reserved

1h = One-shot timer mode

2h = Periodic timer mode

3h = Capture mode

9.5.3 GPTMTBMR Register (offset = 8h) [reset = 0h]

GPTMTBMR is shown in Figure 9-7 and described in Table 9-11.

This register controls the modes for Timer B when it is used individually. When Timer A and Timer B are concatenated, this register is ignored and GPTMTAMR controls the modes for both Timer A and Timer B.

Figure 9-7 GPTMTBMR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTBPLOTBMRSUTBPWMIETBILD
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDTBMIETBCDIRTBAMSTBCMRTBMR
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-11 GPTMTBMR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11TBPLOR/W0h

Timer B PWM Legacy Operation. This bit is only valid in PWM mode.

0h = Legacy operation with CCP pin driven Low when the GPTMTAILR is reloaded after the timer reaches 0.

1h = CCP is driven High when the GPTMTAILR is reloaded after the timer reaches 0.

10TBMRSUR/W0h

GPTM Timer B Match Register Update. If the timer is disabled (TBEN is clear) when this bit is set, GPTMTBMATCHR and GPTMTBPR are updated when the timer is enabled. If the timer is stalled (TBSTALL is set), GPTMTBMATCHR and GPTMTBPR are updated according to the configuration of this bit.

0h = Update the GPTMTBMATCHR register and the GPTMTBPR register, if used, on the next cycle.

1h = Update the GPTMTBMATCHR register and the GPTMTBPR register, if used, on the next time-out.

9TBPWMIER/W0h

GPTM Timer B PWM Interrupt Enable. This bit enables interrupts in PWM mode on rising, falling, or both edges of the CCP output as defined by the TBEVENT field in the GPTMCTL register. In addition, when this bit is set and a capture event occurs, Timer B automatically generates triggers to the ADC and DMA if the trigger capability is enabled, by setting the TBOTE bit in the GPTMCTL register and the CBEDMAEN bit in the GPTMDMAEV register, respectively. This bit is only valid in PWM mode.

0h = Capture event interrupt is disabled.

1h = Capture event is enabled.

8TBILDR/W0h

GPTM Timer B Interval Load Write. The state of this bit has no effect when counting up. The bit descriptions above apply if the timer is enabled and running. If the timer is disabled (TBEN is clear) when this bit is set, GPTMTBR, GPTMTBV, and GPTMTBPS are updated when the timer is enabled. If the timer is stalled (TBSTALL is set), GPTMTBR and GPTMTBPS are updated according to the configuration of this bit.

0h = Update the GPTMTBR and GPTMTBV registers with the value in the GPTMTBILR register on the next cycle. Also update the GPTMTBPS register with the value in the GPTMTBPR register on the next cycle.

1h = Update the GPTMTBR and GPTMTBV registers with the value in the GPTMTBILR register on the next time-out. Also update the GPTMTBPS register with the value in the GPTMTBPR register on the next time-out.

7-6RESERVEDR0h
5TBMIER/W0h

GPTM Timer B Match Interrupt Enable

0h = The match interrupt is disabled for match events. Additionally, triggers to the DMA on match events are prevented.

1h = An interrupt is generated when the match value in the GPTMTBMATCHR register is reached in the one-shot and periodic modes.

4TBCDIRR/W0h

GPTM Timer B Count Direction

0h = The timer counts down.

1h = The timer counts up. When counting up, the timer starts from a value of 0x0. When in PWM mode, the status of this bit is ignored. PWM mode always counts down.

3TBAMSR/W0h

GPTM Timer B Alternate Mode Select. The TBAMS values are defined as follows. To enable PWM mode, clear the TBCMR bit and configure the TBMR field to 0x1 or 0x2.

0h = Capture or compare mode is enabled.

1h = PWM mode is enabled.

2TBCMRR/W0h

GPTM Timer B Capture Mode. The TBCMR values are defined as follows:

0h = Edge-count mode

1h = Edge-time mode

1-0TBMRR/W0h

GPTM Timer B Mode. The TBMR values are defined as follows. The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register.

0h = Reserved

1h = One-shot timer mode

2h = Periodic timer mode

3h = Capture mode

9.5.4 GPTMCTL Register (offset = Ch) [reset = 0h]

GPTMCTL is shown in Figure 9-8 and described in Table 9-12.

Figure 9-8 GPTMCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTBPWMLRESERVEDTBEVENTTBSTALLTBEN
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDTAPWMLRESERVEDTAEVENTTASTALLTAEN
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 9-12 GPTMCTL Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14TBPWMLR/W0h

GPTM Timer B PWM Output Level. The TBPWML values are defined as follows:

0h = Output is unaffected.

1h = Output is inverted.

13-12RESERVEDR0h
11-10TBEVENTR/W0h

GPTM Timer B Event Mode. The TBEVENT values are defined as follows. Note: If PWM output inversion is enabled, edge-detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a positive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal.

0h = Positive edge

1h = Negative edge

2h = Reserved

3h = Both edges

9TBSTALLR/W0h

GPTM Timer B Stall Enable. The TBSTALL values are defined as follows. If the processor is executing normally, the TBSTALL bit is ignored.

0h = Timer B continues counting while the processor is halted by the debugger.

1h = Timer B freezes counting while the processor is halted by the debugger.

8TBENR/W0h

GPTM Timer B Enable. The TBEN values are defined as follows:

0h = Timer B is disabled.

1h = Timer B is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.

7RESERVEDR0h
6TAPWMLR/W0h

GPTM Timer A PWM Output Level. The TAPWML values are defined as follows:

0h = Output is unaffected.

1h = Output is inverted.

5-4RESERVEDR0h
3-2TAEVENTR/W0h

GPTM Timer A Event Mode. The TAEVENT values are defined as follows. If PWM output inversion is enabled, edge-detection interrupt behavior is reversed. Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a positive edge, no event-trigger interrupt asserts. Instead, the interrupt is generated on the negative edge of the PWM signal.

0h = Positive edge

1h = Negative edge

2h = Reserved

3h = Both edges

1TASTALLR/W0h

GPTM Timer A Stall Enable. The TASTALL values are defined as follows. If the processor is executing normally, the TASTALL bit is ignored.

0h = Timer A continues counting while the processor is halted by the debugger.

1h = Timer A freezes counting while the processor is halted by the debugger.

0TAENR/W0h

GPTM Timer A Enable. The TAEN values are defined as follows:

0h = Timer A is disabled.

1h = Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.

9.5.5 GPTMIMR Register (offset = 18h) [reset = 0h]

Register mask: 0h

GPTMIMR is shown in Figure 9-9 and described in Table 9-13.

This register allows software to enable or disable GPTM controller-level interrupts. Setting a bit enables the corresponding interrupt, while clearing a bit disables it.

Figure 9-9 GPTMIMR Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDDMABIMRESERVEDTBMIMCBEIMCBMIMTBTOIM
R-XR/W-XR-XR/W-XR/W-XR/W-XR/W-X
76543210
RESERVEDDMAAIMTAMIMRESERVEDCAEIMCAMIMTATOIM
R-XR/W-XR/W-XR-XR/W-XR/W-XR/W-X
Table 9-13 GPTMIMR Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDRX
13DMABIMR/WX

GPTM Timer B DMA Done Interrupt Mask. The DMABIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

12RESERVEDRX
11TBMIMR/WX

GPTM Timer B Match Interrupt Mask. The TBMIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

10CBEIMR/WX

GPTM Timer B Capture Mode Event Interrupt Mask. The CBEIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

9CBMIMR/WX

GPTM Timer B Capture Mode Match Interrupt Mask. The CBMIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

8TBTOIMR/WX

GPTM Timer B Time-Out Interrupt Mask. The TBTOIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

7-6RESERVEDRX
5DMAAIMR/WX

GPTM Timer A DMA Done Interrupt Mask. The DMAAIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

4TAMIMR/WX

GPTM Timer A Match Interrupt Mask. The TAMIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

3RESERVEDRX
2CAEIMR/WX

GPTM Timer A Capture Mode Event Interrupt Mask. The CAEIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

1CAMIMR/WX

GPTM Timer A Capture Mode Match Interrupt Mask. The CAMIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

0TATOIMR/WX

GPTM Timer A Time-Out Interrupt Mask. The TATOIM values are defined as follows:

0h = Interrupt is disabled.

1h = Interrupt is enabled.

9.5.6 GPTMRIS Register (offset = 1Ch) [reset = 0h]

Register mask: 0h

GPTMRIS is shown in Figure 9-10 and described in Table 9-14.

Figure 9-10 GPTMRIS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDDMABRISRESERVEDTBMRISCBERISCBMRISTBTORIS
R-XR-XR-XR-XR-XR-XR-X
76543210
RESERVEDDMAARISTAMRISRESERVEDCAERISCAMRISTATORIS
R-XR-XR-XR-XR-XR-XR-X
Table 9-14 GPTMRIS Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDRX
13DMABRISRX

GPTM Timer B DMA Done Raw Interrupt Status

0h = The Timer B DMA transfer has not completed.

1h = The Timer B DMA transfer has completed.

12RESERVEDRX
11TBMRISRX

GPTM Timer B Match Raw Interrupt. This bit is cleared by writing 1 to the TBMCINT bit in the GPTMICR register.

0h = The match value has not been reached.

1h = The TBMIE bit is set in the GPTMTBMR register, and the match values in the GPTMTBMATCHR and (optionally) GPTMTBPMR registers have been reached when configured in one-shot or periodic mode.

10CBERISRX

GPTM Timer B Capture Mode Event Raw Interrupt. This bit is cleared by writing 1 to the CBECINT bit in the GPTMICR register.

0h = The capture mode event for Timer B has not occurred.

1h = A capture mode event has occurred for Timer B. This interrupt asserts when the subtimer is configured in input edge-time mode.

9CBMRISRX

GPTM Timer B Capture Mode Match Raw Interrupt. This bit is cleared by writing 1 to the CBMCINT bit in the GPTMICR register.

0h = The capture mode match for Timer B has not occurred.

1h = The capture mode match has occurred for Timer B. This interrupt asserts when the values in the GPTMTBR and GPTMTBPR match the values in the GPTMTBMATCHR and GPTMTBPMR when configured in input edge-time mode.

8TBTORISRX

GPTM Timer B Time-Out Raw Interrupt. This bit is cleared by writing 1 to the TBTOCINT bit in the GPTMICR register.

0h = Timer B has not timed out.

1h = Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches the count limit (0 or the value loaded into GPTMTBILR, depending on the count direction).

7-6RESERVEDRX
5DMAARISRX

GPTM Timer A DMA Done Raw Interrupt Status

0h = The Timer A DMA transfer has not completed.

1h = The Timer A DMA transfer has completed.

4TAMRISRX

GPTM Timer A Match Raw Interrupt. This bit is cleared by writing 1 to the TAMCINT bit in the GPTMICR register.

0h = The match value has not been reached.

1h = The TAMIE bit is set in the GPTMTAMR register, and the match value in the GPTMTAMATCHR and (optionally) GPTMTAPMR registers have been reached when configured in one-shot or periodic mode.

3RESERVEDRX
2CAERISRX

GPTM Timer A Capture Mode Event Raw Interrupt. This bit is cleared by writing 1 to the CAECINT bit in the GPTMICR register.

0h = The capture mode event for Timer A has not occurred.

1h = A capture mode event has occurred for Timer A. This interrupt asserts when the subtimer is configured in input edge-time mode.

1CAMRISRX

GPTM Timer A Capture Mode Match Raw Interrupt. This bit is cleared by writing 1 to the CAMCINT bit in the GPTMICR register.

0h = The capture mode match for Timer A has not occurred.

1h = A capture mode match has occurred for Timer A. This interrupt asserts when the values in the GPTMTAR and GPTMTAPR match the values in the GPTMTAMATCHR and GPTMTAPMR when configured in input edge-time mode.

0TATORISRX

GPTM Timer A Time-Out Raw Interrupt. This bit is cleared by writing 1 to the TATOCINT bit in the GPTMICR register.

0h = Timer A has not timed out.

1h = Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches its count limit (0 or the value loaded into GPTMTAILR, depending on the count direction).

9.5.7 GPTMMIS Register (offset = 20h) [reset = 0h]

Register mask: 0h

GPTMMIS is shown in Figure 9-11 and described in Table 9-15.

Figure 9-11 GPTMMIS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDDMABMISRESERVEDTBMMISCBEMISCBMMISTBTOMIS
R-XR-XR-XR-XR-XR-XR-X
76543210
RESERVEDDMAAMISTAMMISRESERVEDCAEMISCAMMISTATOMIS
R-XR-XR-XR-XR-XR-XR-X
Table 9-15 GPTMMIS Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDRX
13DMABMISRX

GPTM Timer B DMA Done Masked Interrupt. This bit is cleared by writing 1 to the DMABINT bit in the GPTMICR register.

0h = A Timer B DMA done interrupt has not occurred or is masked.

1h = An unmasked Timer B DMA done interrupt has occurred.

12RESERVEDRX
11TBMMISRX

GPTM Timer B Match Masked Interrupt. This bit is cleared by writing 1 to the TBMCINT bit in the GPTMICR register.

0h = A Timer B mode match interrupt has not occurred or is masked.

1h = An unmasked Timer B mode match interrupt has occurred.

10CBEMISRX

GPTM Timer B Capture Mode Event Masked Interrupt. This bit is cleared by writing 1 to the CBECINT bit in the GPTMICR register.

0h = A Capture B event interrupt has not occurred or is masked.

1h = An unmasked Capture B event interrupt has occurred.

9CBMMISRX

GPTM Timer B Capture Mode Match Masked Interrupt. This bit is cleared by writing 1 to the CBMCINT bit in the GPTMICR register.

0h = A Capture B mode match interrupt has not occurred or is masked.

1h = An unmasked Capture B match interrupt has occurred.

8TBTOMISRX

GPTM Timer B Time-Out Masked Interrupt. This bit is cleared by writing 1 to the TBTOCINT bit in the GPTMICR register.

0h = A Timer B time-out interrupt has not occurred or is masked.

1h = An unmasked Timer B time-out interrupt has occurred.

7-6RESERVEDRX
5DMAAMISRX

GPTM Timer A DMA Done Masked Interrupt. This bit is cleared by writing 1 to the DMAAINT bit in the GPTMICR register.

0h = A Timer A DMA done interrupt has not occurred or is masked.

1h = An unmasked Timer A DMA done interrupt has occurred.

4TAMMISRX

GPTM Timer A Match Masked Interrupt. This bit is cleared by writing 1 to the TAMCINT bit in the GPTMICR register.

0h = A Timer A mode match interrupt has not occurred or is masked.

1h = An unmasked Timer A mode match interrupt has occurred.

3RESERVEDRX
2CAEMISRX

GPTM Timer A Capture Mode Event Masked Interrupt. This bit is cleared by writing 1 to the CAECINT bit in the GPTMICR register.

0h = A Capture A event interrupt has not occurred or is masked.

1h = An unmasked Capture A event interrupt has occurred.

1CAMMISRX

GPTM Timer A Capture Mode Match Masked Interrupt. This bit is cleared by writing 1 to the CAMCINT bit in the GPTMICR register.

0h = A Capture A mode match interrupt has not occurred or is masked.

1h = An unmasked Capture A match interrupt has occurred.

0TATOMISRX

GPTM Timer A Time-Out Masked Interrupt. This bit is cleared by writing 1 to the TATOCINT bit in the GPTMICR register.

0h = A Timer A time-out interrupt has not occurred or is masked.

1h = An unmasked Timer A time-out interrupt has occurred.

9.5.8 GPTMICR Register (offset = 24h) [reset = 0h]

Register mask: 0h

GPTMICR is shown in Figure 9-12 and described in Table 9-16.

This register clears the status bits in the GPTMRIS and GPTMMIS registers. Writing 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers.

Figure 9-12 GPTMICR Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDDMABINTRESERVEDTBMCINTCBECINTCBMCINTTBTOCINT
R-XW1C-XR-XW1C-XW1C-XW1C-XW1C-X
76543210
RESERVEDDMAAINTTAMCINTRESERVEDCAECINTCAMCINTTATOCINT
R-XW1C-XW1C-XR-XW1C-XW1C-XW1C-X
Table 9-16 GPTMICR Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDRX
13DMABINTW1CX

GPTM Timer B DMA Done Interrupt Clear. Writing 1 to this bit clears the DMABRIS bit in the GPTMRIS register and the DMABMIS bit in the GPTMMIS register.

12RESERVEDRX
11TBMCINTW1CX

GPTM Timer B Match Interrupt Clear. Writing 1 to this bit clears the TBMRIS bit in the GPTMRIS register and the TBMMIS bit in the GPTMMIS register.

10CBECINTW1CX

GPTM Timer B Capture Mode Event Interrupt Clear. Writing 1 to this bit clears the CBERIS bit in the GPTMRIS register and the CBEMIS bit in the GPTMMIS register.

9CBMCINTW1CX

GPTM Timer B Capture Mode Match Interrupt Clear. Writing 1 to this bit clears the CBMRIS bit in the GPTMRIS register and the CBMMIS bit in the GPTMMIS register.

8TBTOCINTW1CX

GPTM Timer B Time-Out Interrupt Clear. Writing 1 to this bit clears the TBTORIS bit in the GPTMRIS register and the TBTOMIS bit in the GPTMMIS register.

7-6RESERVEDRX
5DMAAINTW1CX

GPTM Timer A DMA Done Interrupt Clear. Writing 1 to this bit clears the DMAARIS bit in the GPTMRIS register and the DMAAMIS bit in the GPTMMIS register.

4TAMCINTW1CX

GPTM Timer A Match Interrupt Clear. Writing 1 to this bit clears the TAMRIS bit in the GPTMRIS register and the TAMMIS bit in the GPTMMIS register.

3RESERVEDRX
2CAECINTW1CX

GPTM Timer A Capture Mode Event Interrupt Clear. Writing 1 to this bit clears the CAERIS bit in the GPTMRIS register and the CAEMIS bit in the GPTMMIS register.

1CAMCINTW1CX

GPTM Timer A Capture Mode Match Interrupt Clear. Writing 1 to this bit clears the CAMRIS bit in the GPTMRIS register and the CAMMIS bit in the GPTMMIS register.

0TATOCINTW1CX

GPTM Timer A Time-Out Raw Interrupt. Writing 1 to this bit clears the TATORIS bit in the GPTMRIS register and the TATOMIS bit in the GPTMMIS register.

9.5.9 GPTMTAILR Register (offset = 28h) [reset = FFFFFFFFh]

GPTMTAILR is shown in Figure 9-13 and described in Table 9-17.

When a GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16 bits correspond to the contents of the GPTM Timer B Interval Load (GPTMTBILR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR.

Figure 9-13 GPTMTAILR Register
313029282726252423222120191817161514131211109876543210
TAILR
R/W-FFFFFFFFh
Table 9-17 GPTMTAILR Register Field Descriptions
BitFieldTypeResetDescription
31-0TAILRR/WFFFFFFFFh

GPTM Timer A Interval Load Register. Writing this field loads the counter for Timer A. A read returns the current value of GPTMTAILR.

9.5.10 GPTMTBILR Register (offset = 2Ch) [reset = FFFFh]

GPTMTBILR is shown in Figure 9-14 and described in Table 9-18.

When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAILR register. Reads from this register return the current value of Timer B, and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load value. Bits 31:16 are reserved in both cases.

Figure 9-14 GPTMTBILR Register
313029282726252423222120191817161514131211109876543210
TBILR
R/W-FFFFh
Table 9-18 GPTMTBILR Register Field Descriptions
BitFieldTypeResetDescription
31-0TBILRR/WFFFFh

GPTM Timer B Interval Load Register. Writing this field loads the counter for Timer B. A read returns the current value of GPTMTBILR. When a 16/32-bit GPTM is in 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR.

9.5.11 GPTMTAMATCHR Register (offset = 30h) [reset = FFFFFFFFh]

GPTMTAMATCHR is shown in Figure 9-15 and described in Table 9-19.

When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAMATCHR appears as a 32-bit register (the upper 16 bits correspond to the contents of the GPTM Timer B Match (GPTMTBMATCHR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBMATCHR.

Figure 9-15 GPTMTAMATCHR Register
313029282726252423222120191817161514131211109876543210
TAMR
R/W-FFFFFFFFh
Table 9-19 GPTMTAMATCHR Register Field Descriptions
BitFieldTypeResetDescription
31-0TAMRR/WFFFFFFFFh

GPTM Timer A Match Register. This value is compared to the GPTMTAR register to determine match events.

9.5.12 GPTMTBMATCHR Register (offset = 34h) [reset = FFFFh]

GPTMTBMATCHR is shown in Figure 9-16 and described in Table 9-20.

When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAMATCHR register. Reads from this register return the current match value of Timer B, and writes are ignored. In a 16-bit mode, bits 15:0 are used for the match value. Bits 31:16 are reserved in both cases.

Figure 9-16 GPTMTBMATCHR Register
313029282726252423222120191817161514131211109876543210
TBMR
R/W-FFFFh
Table 9-20 GPTMTBMATCHR Register Field Descriptions
BitFieldTypeResetDescription
31-0TBMRR/WFFFFh

GPTM Timer B Match Register. This value is compared to the GPTMTBR register to determine match events.

9.5.13 GPTMTAPR Register (offset = 38h) [reset = 0h]

GPTMTAPR is shown in Figure 9-17 and described in Table 9-21.

This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the GPTMTAR and GPTMTAV registers are incremented. In all other individual or split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPTM.

Figure 9-17 GPTMTAPR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTAPSR
R-XR/W-0h
Table 9-21 GPTMTAPR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7-0TAPSRR/W0h

GPTM Timer A Prescale. The register loads this value on a write. A read returns the current value of the register. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler.

9.5.14 GPTMTBPR Register (offset = 3Ch) [reset = 0h]

GPTMTBPR is shown in Figure 9-18 and described in Table 9-22.

This register allows software to extend the range of the timers when they are used individually. When in one-shot or periodic down count modes, this register acts as a true prescaler for the timer counter. When acting as a true prescaler, the prescaler counts down to 0 before the value in the GPTMTBR and GPTMTBPR registers are incremented. In all other individual or split modes, this register is a linear extension of the upper range of the timer counter, holding bits 23:16 in the 16-bit modes of the 16/32-bit GPTM.

Figure 9-18 GPTMTBPR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPSR
R-XR/W-0h
Table 9-22 GPTMTBPR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7-0TBPSRR/W0h

GPTM Timer B Prescale. The register loads this value on a write. A read returns the current value of this register. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler.

9.5.15 GPTMTAPMR Register (offset = 40h) [reset = 0h]

GPTMTAPMR is shown in Figure 9-19 and described in Table 9-23.

This register allows software to extend the range of the GPTMTAMATCHR when the timers are used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM.

Figure 9-19 GPTMTAPMR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTAPSMR
R-XR/W-0h
Table 9-23 GPTMTAPMR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7-0TAPSMRR/W0h

GPTM Timer A Prescale Match. This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. For the 16/32-bit GPTM, this field contains the entire 8-bit prescaler match value.

9.5.16 GPTMTBPMR Register (offset = 44h) [reset = 0h]

GPTMTBPMR is shown in Figure 9-20 and described in Table 9-24.

This register allows software to extend the range of the GPTMTBMATCHR when the timers are used individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM.

Figure 9-20 GPTMTBPMR Register
313029282726252423222120191817161514131211109876543210
RESERVEDTBPSMR
R-XR/W-0h
Table 9-24 GPTMTBPMR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7-0TBPSMRR/W0h

GPTM Timer B Prescale Match. This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler.

9.5.17 GPTMTAR Register (offset = 48h) [reset = FFFFFFFFh]

GPTMTAR is shown in Figure 9-21 and described in Table 9-25.

When a GPTM is configured to one of the 32-bit modes, GPTMTAR appears as a 32-bit register (the upper 16 bits correspond to the contents of the GPTM Timer B (GPTMTBR) register). In the 16-bit input edge-count, input edge-time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit one-shot and periodic modes, read bits [23:16] in the GPTMTAV register. To read the value of the prescalar in periodic snapshot mode, read the Timer A Prescale Snapshot (GPTMTAPS) register.

Figure 9-21 GPTMTAR Register
313029282726252423222120191817161514131211109876543210
TAR
R-FFFFFFFFh
Table 9-25 GPTMTAR Register Field Descriptions
BitFieldTypeResetDescription
31-0TARRFFFFFFFFh

GPTM Timer A Register. A read returns the current value of the GPTM Timer A Count register, in all cases except for input edge-count and time modes. In the input edge-count mode, this register contains the number of edges that have occurred. In the input edge-time mode, this register contains the time at which the last edge event took place.

9.5.18 GPTMTBR Register (offset = 4Ch) [reset = FFFFh]

GPTMTBR is shown in Figure 9-22 and described in Table 9-26.

When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAR register. Reads from this register return the current value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of the prescaler in input edge-count, input edge-time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To read the value of the prescaler in 16-bit one-shot and periodic modes, read bits [23:16] in the GPTMTBV register. To read the value of the prescalar in periodic snapshot mode, read the Timer B Prescale Snapshot (GPTMTBPS) register.

Figure 9-22 GPTMTBR Register
313029282726252423222120191817161514131211109876543210
TBR
R-FFFFh
Table 9-26 GPTMTBR Register Field Descriptions
BitFieldTypeResetDescription
31-0TBRRFFFFh

GPTM Timer B Register. A read returns the current value of the GPTM Timer B Count register, in all cases except for input edge-count and time modes. In the input edge-count mode, this register contains the number of edges that have occurred. In the input edge-time mode, this register contains the time at which the last edge event took place.

9.5.19 GPTMTAV Register (offset = 50h) [reset = FFFFFFFFh]

GPTMTAV is shown in Figure 9-23 and described in Table 9-27.

When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAV appears as a 32-bit register (the upper 16 bits correspond to the contents of the GPTM Timer B Value (GPTMTBV) register). In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in input edge-count, input edge-time, PWM, and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0.

Figure 9-23 GPTMTAV Register
313029282726252423222120191817161514131211109876543210
TAV
R/W-FFFFFFFFh
Table 9-27 GPTMTAV Register Field Descriptions
BitFieldTypeResetDescription
31-0TAVR/WFFFFFFFFh

GPTM Timer A Value. A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. Note: In 16-bit mode, only the lower 16 bits of the GPTMTAV register can be written with a new value. Writes to the prescaler bits have no effect.

9.5.20 GPTMTBV Register (offset = 54h) [reset = FFFFh]

GPTMTBV is shown in Figure 9-24 and described in Table 9-28.

When a 16/32-bit GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are loaded into the upper 16 bits of the GPTMTAV register. Reads from this register return the current free-running value of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count in input edge-count, input edge-time, PWM, and one-shot or periodic up count modes. In one-shot or periodic down count modes, the prescaler stored in 23:16 is a true prescaler, meaning bits 23:16 count down before decrementing the value in bits 15:0. The prescaler in bits 31:24 always reads as 0.

Figure 9-24 GPTMTBV Register
313029282726252423222120191817161514131211109876543210
TBV
R/W-FFFFh
Table 9-28 GPTMTBV Register Field Descriptions
BitFieldTypeResetDescription
31-0TBVR/WFFFFh

GPTM Timer B Value. A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. In 16-bit mode, only the lower 16 bits of the GPTMTBV register can be written with a new value. Writes to the prescaler bits have no effect.

9.5.21 GPTMDMAEV Register (offset = 6Ch) [reset = 0h]

GPTMDMAEV is shown in Figure 9-25 and described in Table 9-29.

This register allows software to enable and disable GPTM DMA trigger events. Setting a bit enables the corresponding DMA trigger, while clearing a bit disables it.

Figure 9-25 GPTMDMAEV Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTBMDMAENCBEDMAENCBMDMAENTBTODMAEN
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDTAMDMAENRTCDMAENCAEDMAENCAMDMAENTATODMAEN
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 9-29 GPTMDMAEV Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11TBMDMAENR/W0h

GPTM B Mode Match Event DMA Trigger Enable. When this bit is enabled, a Timer B dma_req signal is sent to the DMA when a mode match has occurred.

0h = Timer B mode match DMA trigger is disabled.

1h = Timer B DMA mode match trigger is enabled

10CBEDMAENR/W0h

GPTM B Capture Event DMA Trigger Enable. When this bit is enabled, a Timer B dma_req signal is sent to the DMA when a capture event has occurred.

0h = Timer B capture event DMA trigger is disabled.

1h = Timer B capture event DMA trigger is enabled.

9CBMDMAENR/W0h

GPTM B Capture Match Event DMA Trigger Enable. When this bit is enabled, a Timer B dma_req signal is sent to the DMA when a capture match event has occurred.

0h = Timer B capture match DMA trigger is disabled.

1h = Timer B capture match DMA trigger is enabled

8TBTODMAENR/W0h

GPTM B Time-Out Event DMA Trigger Enable. When this bit is enabled, a Timer B dma_req signal is sent to the DMA on a time-out event.

0h = Timer B time-out DMA trigger is disabled.

1h = Timer B time-out DMA trigger is enabled.

7-5RESERVEDR0h
4TAMDMAENR/W0h

GPTM A Mode Match Event DMA Trigger Enable. When this bit is enabled, a Timer A dma_req signal is sent to the DMA when a mode match has occurred.

0h = Timer A mode match DMA trigger is disabled.

1h = Timer A DMA mode match trigger is enabled.

3RTCDMAENR/W0h

GPTM A RTC Match Event DMA Trigger Enable. When this bit is enabled, a Timer A dma_req signal is sent to the DMA when a RTC match has occurred.

0h = Timer A RTC match DMA trigger is disabled.

1h = Timer A RTC match DMA trigger is enabled.

2CAEDMAENR/W0h

GPTM A Capture Event DMA Trigger Enable. When this bit is enabled, a Timer A dma_req signal is sent to the DMA when a capture event has occurred.

0h = Timer A capture event DMA trigger is disabled.

1h = Timer A capture event DMA trigger is enabled.

1CAMDMAENR/W0h

GPTM A Capture Match Event DMA Trigger Enable. When this bit is enabled, a Timer A dma_req signal is sent to the DMA when a capture match event has occurred.

0h = Timer A capture match DMA trigger is disabled.

1h = Timer A capture match DMA trigger is enabled.

0TATODMAENR/W0h

GPTM A Time-Out Event DMA Trigger Enable. When this bit is enabled, a Timer A dma_req signal is sent to the DMA on a time-out event.

0h = Timer A time-out DMA trigger is disabled.

1h = Timer A time-out DMA trigger is enabled.