SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

15.6 PRCM Registers

Table 15-3 lists the memory-mapped registers for the PRCM. All register offset addresses not listed in Table 15-3 should be considered as reserved locations, and the register contents should not be modified.

Table 15-3 PRCM Registers
OffsetAcronymRegister NameSection
0hCAMCLKCFGSection 15.6.1
4hCAMCLKENSection 15.6.2
8hCAMSWRSTSection 15.6.3
14hMCASPCLKENSection 15.6.4
18hMCASPSWRSTSection 15.6.5
20hSDIOMCLKCFGSection 15.6.6
24hSDIOMCLKENSection 15.6.7
28hSDIOMSWRSTSection 15.6.8
2ChAPSPICLKCFGSection 15.6.9
30hAPSPICLKENSection 15.6.10
34hAPSPISWRSTSection 15.6.11
48hDMACLKENSection 15.6.12
4ChDMASWRSTSection 15.6.13
50hGPIO0CLKENSection 15.6.14
54hGPIO0SWRSTSection 15.6.15
58hGPIO1CLKENSection 15.6.16
5ChGPIO1SWRSTSection 15.6.17
60hGPIO2CLKENSection 15.6.18
64hGPIO2SWRSTSection 15.6.19
68hGPIO3CLKENSection 15.6.20
6ChGPIO3SWRSTSection 15.6.21
70hGPIO4CLKENSection 15.6.22
74hGPIO4SWRSTSection 15.6.23
78hWDTCLKENSection 15.6.24
7ChWDTSWRSTSection 15.6.25
80hUART0CLKENSection 15.6.26
84hUART0SWRSTSection 15.6.27
88hUART1CLKENSection 15.6.28
8ChUART1SWRSTSection 15.6.29
90hGPT0CLKCFGSection 15.6.30
94hGPT0SWRSTSection 15.6.31
98hGPT1CLKENSection 15.6.32
9ChGPT1SWRSTSection 15.6.33
A0hGPT2CLKENSection 15.6.34
A4hGPT2SWRSTSection 15.6.35
A8hGPT3CLKENSection 15.6.36
AChGPT3SWRSTSection 15.6.37
B0hMCASPCLKCFG0Section 15.6.38
B4hMCASPCLKCFG1Section 15.6.39
D8hI2CLCKENSection 15.6.40
DChI2CSWRSTSection 15.6.41
E4hLPDSREQSection 15.6.42
EChTURBOREQSection 15.6.43
108hDSLPWAKECFGSection 15.6.44
10ChDSLPTIMRCFGSection 15.6.45
110hSLPWAKEENSection 15.6.46
114hSLPTMRCFGSection 15.6.47
118hWAKENWPSection 15.6.48
120hRCM_ISSection 15.6.49
124hRCM_IENSection 15.6.50

15.6.1 CAMCLKCFG Register (offset = 0h) [reset = 0h]

CAMCLKCFG is shown in Figure 15-3 and described in Table 15-4.

Figure 15-3 CAMCLKCFG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDDIVOFFTIMNU1DIVONTIM
R-0hR/W-0hR-0hR/W-0h
Table 15-4 CAMCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0h
10-8DIVOFFTIMR/W0h

CAMERA_PLLCKDIV_OFF_TIME Configuration of OFF-TIME for dividing PLL clock (240 MHz) in generation of Camera func-clk:

000h = 1

001h = 2

010h = 3

011h = 4

100h = 5

101h = 6

110h = 7

111h = 8

7-3NU1R0h
2-0DIVONTIMR/W0h

CAMERA_PLLCKDIV_ON_TIME Configuration of ON-TIME for dividing PLL clock (240 MHz) in generation of Camera func-clk:

000h = 1

001h = 2

010h = 3

011h = 4

100h = 5

101h = 6

110h = 7

111h = 8

15.6.2 CAMCLKEN Register (offset = 4h) [reset = 0h]

CAMCLKEN is shown in Figure 15-4 and described in Table 15-5.

Figure 15-4 CAMCLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
NU1DSLPCLKEN
R-0hR-0h
15141312111098
NU2SLPCLKEN
R-0hR/W-0h
76543210
NU3RUNCLKEN
R-0hR/W-0h
Table 15-5 CAMCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23-17NU1R0h
16DSLPCLKENR0h

CAMERA_DSLP_CLK_ENABLE

0h = Disable camera clock during deep-sleep mode

15-9NU2R0h
8SLPCLKENR/W0h

CAMERA_SLP_CLK_ENABLE

0h = Disable camera clock during sleep mode

1h = Enable camera clock during sleep mode

7-1NU3R0h
0RUNCLKENR/W0h

CAMERA_RUN_CLK_ENABLE

0h = Disable camera clock during run mode

1h = Enable camera clock during run mode

15.6.3 CAMSWRST Register (offset = 8h) [reset = 0h]

CAMSWRST is shown in Figure 15-5 and described in Table 15-6.

Figure 15-5 CAMSWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-6 CAMSWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

CAMERA_ENABLED_STATUS

0h = Camera clocks/resets are disabled

1h = Camera clocks/resets are enabled

0SWRSTR/W0h

CAMERA_SOFT_RESET

0h = Deassert reset for Camera-core

1h = Assert reset for Camera-core

15.6.4 MCASPCLKEN Register (offset = 14h) [reset = 0h]

MCASPCLKEN is shown in Figure 15-6 and described in Table 15-7.

Figure 15-6 MCASPCLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
NU1DSLPCLKEN
R-0hR-0h
15141312111098
NU2SLPCLKEN
R-0hR/W-0h
76543210
NU3RUNCLKEN
R-0hR/W-0h
Table 15-7 MCASPCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23-17NU1R0h
16DSLPCLKENR0h

MCASP_DSLP_CLK_ENABLE

0h = Disable MCASP clock during deep-sleep mode

15-9NU2R0h
8SLPCLKENR/W0h

MCASP_SLP_CLK_ENABLE

0h = Disable MCASP clock during sleep mode

1h = Enable MCASP clock during sleep mode

7-1NU3R0h
0RUNCLKENR/W0h

MCASP_RUN_CLK_ENABLE

0h = Disable MCASP clock during run mode

1h = Enable MCASP clock during run mode

15.6.5 MCASPSWRST Register (offset = 18h) [reset = 0h]

MCASPSWRST is shown in Figure 15-7 and described in Table 15-8.

Figure 15-7 MCASPSWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-8 MCASPSWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

MCASP_ENABLED_STATUS

0h = MCASP Clocks/resets are disabled

1h = MCASP Clocks/resets are enabled

0SWRSTR/W0h

MCASP_SOFT_RESET

0h = Deassert reset for MCASP-core

1h = Assert reset for MCASP-core

15.6.6 SDIOMCLKCFG Register (offset = 20h) [reset = 0h]

SDIOMCLKCFG is shown in Figure 15-8 and described in Table 15-9.

Figure 15-8 SDIOMCLKCFG Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDDIVOFFTIMNU1DIVONTIM
R-0hR/W-0hR-0hR/W-0h
Table 15-9 SDIOMCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0h
10-8DIVOFFTIMR/W0h

MMCHS_PLLCKDIV_OFF_TIME Configuration of OFF-TIME for dividing PLL clock (240 MHz) in generation of MMCHS func-clk:

000h = 1

001h = 2

010h = 3

011h = 4

100h = 5

101h = 6

110h = 7

111h = 8

7-3NU1R0h
2-0DIVONTIMR/W0h

MMCHS_PLLCKDIV_ON_TIME Configuration of ON-TIME for dividing PLL clock (240 MHz) in generation of MMCHS func-clk:

000h = 1

001h = 2

010h = 3

011h = 4

100h = 5

101h = 6

110h = 7

111h = 8

15.6.7 SDIOMCLKEN Register (offset = 24h) [reset = 0h]

SDIOMCLKEN is shown in Figure 15-9 and described in Table 15-10.

Figure 15-9 SDIOMCLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
NU1DSLPCLKEN
R-0hR-0h
15141312111098
NU2SLPCLKEN
R-0hR/W-0h
76543210
NU3RUNCLKEN
R-0hR/W-0h
Table 15-10 SDIOMCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23-17NU1R0h
16DSLPCLKENR0h

MMCHS_DSLP_CLK_ENABLE

0h = Disable MMCHS clock during deep-sleep mode

15-9NU2R0h
8SLPCLKENR/W0h

MMCHS_SLP_CLK_ENABLE

0h = Disable MMCHS clock during sleep mode

1h = Enable MMCHS clock during sleep mode

7-1NU3R0h
0RUNCLKENR/W0h

MMCHS_RUN_CLK_ENABLE

0h = Disable MMCHS clock during run mode

1h = Enable MMCHS clock during run mode

15.6.8 SDIOMSWRST Register (offset = 28h) [reset = 0h]

SDIOMSWRST is shown in Figure 15-10 and described in Table 15-11.

Figure 15-10 SDIOMSWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-11 SDIOMSWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

MMCHS_ENABLED_STATUS

0h = MMCHS clocks and resets are disabled

1h = MMCHS clocks and resets are enabled

0SWRSTR/W0h

MMCHS_SOFT_RESET

0h = Deassert reset for MMCHS-core

1h = Assert reset for MMCHS-core

15.6.9 APSPICLKCFG Register (offset = 2Ch) [reset = 0h]

APSPICLKCFG is shown in Figure 15-11 and described in Table 15-12.

Figure 15-11 APSPICLKCFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDBAUDSEL
R-0hR/W-0h
15141312111098
NU1DIVOFFTIM
R-0hR/W-0h
76543210
NU2DIVONTIM
R-0hR/W-0h
Table 15-12 APSPICLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16BAUDSELR/W0h

MCSPI_A1_BAUD_CLK_SEL

0h = crystal clock is used as baud clock for MCSPI_A1

1h = PLL divclk is used as baud clock for MCSPI_A1.

15-11NU1R0h
10-8DIVOFFTIMR/W0h

MCSPI_A1_PLLCLKDIV_OFF_TIME Configuration of OFF-TIME for dividing PLL clock (240 MHz) in generation of MCSPI_A1 func-clk:

000h = 1

001h = 2

010h = 3

011h = 4

100h = 5

101h = 6

110h = 7

111h = 8

7-3NU2R0h
2-0DIVONTIMR/W0h

MCSPI_A1_PLLCLKDIV_ON_TIME Configuration of ON-TIME for dividing PLL clock (240 MHz) in generation of MCSPI_A1 func-clk:

000h = 1

001h = 2

010h = 3

011h = 4

100h = 5

101h = 6

110h = 7

111h = 8

15.6.10 APSPICLKEN Register (offset = 30h) [reset = 0h]

APSPICLKEN is shown in Figure 15-12 and described in Table 15-13.

Figure 15-12 APSPICLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
NU1DSLPCLKEN
R-0hR-0h
15141312111098
NU2SLPCLKEN
R-0hR/W-0h
76543210
NU3RUNCLKEN
R-0hR/W-0h
Table 15-13 APSPICLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23-17NU1R0h
16DSLPCLKENR0h

MCSPI_A1_DSLP_CLK_ENABLE

0h = Disable MCSPI_A1 clock during deep-sleep mode

15-9NU2R0h
8SLPCLKENR/W0h

MCSPI_A1_SLP_CLK_ENABLE

0h = Disable MCSPI_A1 clock during sleep mode

1h = Enable MCSPI_A1 clock during sleep mode

7-1NU3R0h
0RUNCLKENR/W0h

MCSPI_A1_RUN_CLK_ENABLE

0h = Disable MCSPI_A1 clock during run mode

1h = Enable MCSPI_A1 clock during run mode

15.6.11 APSPISWRST Register (offset = 34h) [reset = 0h]

APSPISWRST is shown in Figure 15-13 and described in Table 15-14.

Figure 15-13 APSPISWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-14 APSPISWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

MCSPI_A1_ENABLED_STATUS

0h = MCSPI_A1 clocks and resets are disabled

1h = MCSPI_A1 clocks and resets are enabled

0SWRSTR/W0h

MCSPI_A1_SOFT_RESET

0h = Deassert reset for MCSPI_A1-core

1h = Assert reset for MCSPI_A1-core

15.6.12 DMACLKEN Register (offset = 48h) [reset = 0h]

DMACLKEN is shown in Figure 15-14 and described in Table 15-15.

Figure 15-14 DMACLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-15 DMACLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

UDMA_A_DSLP_CLK_ENABLE

0h = Disable UDMA_A clock during deep-sleep mode

1h = Enable UDMA_A clock during deep-sleep mode

15-9NU1R0h
8SLPCLKENR/W0h

UDMA_A_SLP_CLK_ENABLE

0h = Disable UDMA_A clock during sleep mode

1h = Enable UDMA_A clock during sleep mode

7-1NU2R0h
0RUNCLKENR/W0h

UDMA_A_RUN_CLK_ENABLE

0h = Disable UDMA_A clock during run mode

1h = Enable UDMA_A clock during run mode

15.6.13 DMASWRST Register (offset = 4Ch) [reset = 0h]

DMASWRST is shown in Figure 15-15 and described in Table 15-16.

Figure 15-15 DMASWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-16 DMASWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

UDMA_A_ENABLED_STATUS

0h = UDMA_A clocks and resets are disabled

1h = UDMA_A clocks and resets are enabled

0SWRSTR/W0h

UDMA_A_SOFT_RESET

0h = Deassert reset for DMA_A

1h = Assert reset for DMA_A

15.6.14 GPIO0CLKEN Register (offset = 50h) [reset = 0h]

GPIO0CLKEN is shown in Figure 15-16 and described in Table 15-17.

Figure 15-16 GPIO0CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-17 GPIO0CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

GPIO_A_DSLP_CLK_ENABLE

0h = Disable GPIO_A clock during deep-sleep mode

1h = Enable GPIO_A clock during deep-sleep mode

15-9NU1R0h
8SLPCLKENR/W0h

GPIO_A_SLP_CLK_ENABLE

0h = Disable GPIO_A clock during sleep mode

1h = Enable GPIO_A clock during sleep mode

7-1NU2R0h
0RUNCLKENR/W0h

GPIO_A_RUN_CLK_ENABLE

0h = Disable GPIO_A clock during run mode

1h = Enable GPIO_A clock during run mode

15.6.15 GPIO0SWRST Register (offset = 54h) [reset = 0h]

GPIO0SWRST is shown in Figure 15-17 and described in Table 15-18.

Figure 15-17 GPIO0SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-18 GPIO0SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

GPIO_A_ENABLED_STATUS

0h = GPIO_A clocks and resets are disabled

1h = GPIO_A clocks and resets are enabled

0SWRSTR/W0h

GPIO_A_SOFT_RESET

0h = Deassert reset for GPIO_A

1h = Assert reset for GPIO_A

15.6.16 GPIO1CLKEN Register (offset = 58h) [reset = 0h]

GPIO1CLKEN is shown in Figure 15-18 and described in Table 15-19.

Figure 15-18 GPIO1CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-19 GPIO1CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

GPIO_B_DSLP_CLK_ENABLE

0h = Disable GPIO_B clock during deep-sleep mode

1h = Enable GPIO_B clock during deep-sleep mode

15-9NU1R0h
8SLPCLKENR/W0h

GPIO_B_SLP_CLK_ENABLE

0h = Disable GPIO_B clock during sleep mode

1h = Enable GPIO_B clock during sleep mode

7-1NU2R0h
0RUNCLKENR/W0h

GPIO_B_RUN_CLK_ENABLE

0h = Disable GPIO_B clock during run mode

1h = Enable GPIO_B clock during run mode

15.6.17 GPIO1SWRST Register (offset = 5Ch) [reset = 0h]

GPIO1SWRST is shown in Figure 15-19 and described in Table 15-20.

Figure 15-19 GPIO1SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-20 GPIO1SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

GPIO_B_ENABLED_STATUS

0h = GPIO_B clocks and resets are disabled

1h = GPIO_B clocks and resets are enabled

0SWRSTR/W0h

GPIO_B_SOFT_RESET

0h = Deassert reset for GPIO_B

1h = Assert reset for GPIO_B

15.6.18 GPIO2CLKEN Register (offset = 60h) [reset = 0h]

GPIO2CLKEN is shown in Figure 15-20 and described in Table 15-21.

Figure 15-20 GPIO2CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-21 GPIO2CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

GPIO_C_DSLP_CLK_ENABLE

0h = Disable GPIO_C clock during deep-sleep mode

1h = Enable GPIO_C clock during deep-sleep mode

15-9NU1R0h
8SLPCLKENR/W0h

GPIO_C_SLP_CLK_ENABLE

0h = Disable GPIO_C clock during sleep mode

1h = Enable GPIO_C clock during sleep mode

7-1NU2R0h
0RUNCLKENR/W0h

GPIO_C_RUN_CLK_ENABLE

0h = Disable GPIO_C clock during run mode

1h = Enable GPIO_C clock during run mode

15.6.19 GPIO2SWRST Register (offset = 64h) [reset = 0h]

GPIO2SWRST is shown in Figure 15-21 and described in Table 15-22.

Figure 15-21 GPIO2SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-22 GPIO2SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

GPIO_C_ENABLED_STATUS

0h = GPIO_C clocks and resets are disabled

1h = GPIO_C clocks and resets are enabled

0SWRSTR/W0h

GPIO_C_SOFT_RESET

0h = Deassert reset for GPIO_C

1h = Assert reset for GPIO_C

15.6.20 GPIO3CLKEN Register (offset = 68h) [reset = 0h]

GPIO3CLKEN is shown in Figure 15-22 and described in Table 15-23.

Figure 15-22 GPIO3CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-23 GPIO3CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

GPIO_D_DSLP_CLK_ENABLE

0h = Disable GPIO_D clock during deep-sleep mode

1h = Enable GPIO_D clock during deep-sleep mode

15-9NU1R0h
8SLPCLKENR/W0h

GPIO_D_SLP_CLK_ENABLE

0h = Disable GPIO_D clock during sleep mode

1h = Enable GPIO_D clock during sleep mode

7-1NU2R0h
0RUNCLKENR/W0h

GPIO_D_RUN_CLK_ENABLE

0h = Disable GPIO_D clock during run mode

1h = Enable GPIO_D clock during run mode

15.6.21 GPIO3SWRST Register (offset = 6Ch) [reset = 0h]

GPIO3SWRST is shown in Figure 15-23 and described in Table 15-24.

Figure 15-23 GPIO3SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-24 GPIO3SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

GPIO_D_ENABLED_STATUS

0h = GPIO_D clocks and resets are disabled

1h = GPIO_D clocks and resets are enabled

0SWRSTR/W0h

GPIO_D_SOFT_RESET

0h = Deassert reset for GPIO_D

1h = Assert reset for GPIO_D

15.6.22 GPIO4CLKEN Register (offset = 70h) [reset = 0h]

GPIO4CLKEN is shown in Figure 15-24 and described in Table 15-25.

Figure 15-24 GPIO4CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-25 GPIO4CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

GPIO_E_DSLP_CLK_ENABLE

0h = Disable GPIO_E clock during deep-sleep mode

1h = Enable GPIO_E clock during deep-sleep mode

15-9NU1R0h
8SLPCLKENR/W0h

GPIO_E_SLP_CLK_ENABLE

0h = Disable GPIO_E clock during sleep mode

1h = Enable GPIO_E clock during sleep mode

7-1NU2R0h
0RUNCLKENR/W0h

GPIO_E_RUN_CLK_ENABLE

0h = Disable GPIO_E clock during run mode

1h = Enable GPIO_E clock during run mode

15.6.23 GPIO4SWRST Register (offset = 74h) [reset = 0h]

GPIO4SWRST is shown in Figure 15-25 and described in Table 15-26.

Figure 15-25 GPIO4SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-26 GPIO4SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

GPIO_E_ENABLED_STATUS

0h = GPIO_E clocks and resets are disabled

1h = GPIO_E clocks and resets are enabled

0SWRSTR/W0h

GPIO_E_SOFT_RESET

0h = Deassert reset for GPIO_E

1h = Assert reset for GPIO_E

15.6.24 WDTCLKEN Register (offset = 78h) [reset = 0h]

WDTCLKEN is shown in Figure 15-26 and described in Table 15-27.

Figure 15-26 WDTCLKEN Register
3130292827262524
RESERVEDBAUDCLKSEL
R-0hR/W-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-27 WDTCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25-24BAUDCLKSELR/W0h

WDOG_A_BAUD_CLK_SEL

00h = Sysclk

01h = REF_CLK (38.4 MHz)

10/11"h = Slow_clk

23-17RESERVEDR0h
16DSLPCLKENR/W0h

WDOG_A_DSLP_CLK_ENABLE

0h = Disable WDOG_A clock during deep-sleep mode

1h = Enable WDOG_A clock during deep-sleep mode

15-9NU1R0h
8SLPCLKENR/W0h

WDOG_A_SLP_CLK_ENABLE

0h = Disable WDOG_A clock during sleep mode

1h = Enable WDOG_A clock during sleep mode

7-1NU2R0h
0RUNCLKENR/W0h

WDOG_A_RUN_CLK_ENABLE

0h = Disable WDOG_A clock during run mode

1h = Enable WDOG_A clock during run mode

15.6.25 WDTSWRST Register (offset = 7Ch) [reset = 0h]

WDTSWRST is shown in Figure 15-27 and described in Table 15-28.

Figure 15-27 WDTSWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-28 WDTSWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

WDOG_A_ENABLED_STATUS

0h = WDOG_A clocks and resets are disabled

1h = WDOG_A clocks and resets are enabled

0SWRSTR/W0h

WDOG_A_SOFT_RESET

0h = Deassert reset for WDOG_A

1h = Assert reset for WDOG_A

15.6.26 UART0CLKEN Register (offset = 80h) [reset = 0h]

UART0CLKEN is shown in Figure 15-28 and described in Table 15-29.

Figure 15-28 UART0CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDUART0DSLPCLKEN
R-0hR/W-0h
15141312111098
NU1UART0SLPCLKEN
R-0hR/W-0h
76543210
NU2UART0RCLKEN
R-0hR/W-0h
Table 15-29 UART0CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16UART0DSLPCLKENR/W0h

UART_A0_DSLP_CLK_ENABLE

0h = Disable UART_A0 clock during deep-sleep mode

1h = Enable UART_A0 clock during deep-sleep mode

15-9NU1R0h
8UART0SLPCLKENR/W0h

UART_A0_SLP_CLK_ENABLE

0h = Disable UART_A0 clock during sleep mode

1h = Enable UART_A0 clock during sleep mode

7-1NU2R0h
0UART0RCLKENR/W0h

UART_A0_RUN_CLK_ENABLE

0h = Disable UART_A0 clock during run mode

1h = Enable UART_A0 clock during run mode

15.6.27 UART0SWRST Register (offset = 84h) [reset = 0h]

UART0SWRST is shown in Figure 15-29 and described in Table 15-30.

Figure 15-29 UART0SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-30 UART0SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

UART_A0_ENABLED_STATUS

0h = UART_A0 clocks and resets are disabled

1h = UART_A0 clocks and resets are enabled

0SWRSTR/W0h

UART_A0_SOFT_RESET

0h = Deassert reset for UART_A0

1h = Assert reset for UART_A0

15.6.28 UART1CLKEN Register (offset = 88h) [reset = 0h]

UART1CLKEN is shown in Figure 15-30 and described in Table 15-31.

Figure 15-30 UART1CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-31 UART1CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

UART_A1_DSLP_CLK_ENABLE

0h = Disable UART_A1 clock during deep-sleep mode

1h = Enable UART_A1 clock during deep-sleep mode

15-9NU1R0h
8SLPCLKENR/W0h

UART_A1_SLP_CLK_ENABLE

0h = Disable UART_A1 clock during sleep mode

1h = Enable UART_A1 clock during sleep mode

7-1NU2R0h
0RUNCLKENR/W0h

UART_A1_RUN_CLK_ENABLE

0h = Disable UART_A1 clock during run mode

1h = Enable UART_A1 clock during run mode

15.6.29 UART1SWRST Register (offset = 8Ch) [reset = 0h]

UART1SWRST is shown in Figure 15-31 and described in Table 15-32.

Figure 15-31 UART1SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-32 UART1SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

UART_A1_ENABLED_STATUS

0h = UART_A1 clocks and resets are disabled

1h = UART_A1 clocks and resets are enabled

0SWRSTR/W0h

UART_A1_SOFT_RESET

0h = Deassert the soft reset for UART_A1

1h = Assert the soft reset for UART_A1

15.6.30 GPT0CLKCFG Register (offset = 90h) [reset = 0h]

GPT0CLKCFG is shown in Figure 15-32 and described in Table 15-33.

Figure 15-32 GPT0CLKCFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-33 GPT0CLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

GPT_A0_DSLP_CLK_ENABLE

0h = Disable the GPT_A0 clock during deep-sleep

1h = Enable the GPT_A0 clock during deep-sleep

15-9NU1R0h
8SLPCLKENR/W0h

GPT_A0_SLP_CLK_ENABLE

0h = Disable the GPT_A0 clock during sleep

1h = Enable the GPT_A0 clock during sleep

7-1NU2R0h
0RUNCLKENR/W0h

GPT_A0_RUN_CLK_ENABLE

0h = Disable the GPT_A0 clock during run

1h = Enable the GPT_A0 clock during run

15.6.31 GPT0SWRST Register (offset = 94h) [reset = 0h]

GPT0SWRST is shown in Figure 15-33 and described in Table 15-34.

Figure 15-33 GPT0SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-34 GPT0SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

GPT_A0_ENABLED_STATUS

0h = GPT_A0 clocks and resets are disabled

1h = GPT_A0 clocks and resets are enabled

0SWRSTR/W0h

GPT_A0_SOFT_RESET

0h = Deassert the soft reset for GPT_A0

1h = Assert the soft reset for GPT_A0

15.6.32 GPT1CLKEN Register (offset = 98h) [reset = 0h]

GPT1CLKEN is shown in Figure 15-34 and described in Table 15-35.

Figure 15-34 GPT1CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-35 GPT1CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

GPT_A1_DSLP_CLK_ENABLE

0h = Disable the GPT_A1 clock during deep-sleep

1h = Enable the GPT_A1 clock during deep-sleep

15-9NU1R0h
8SLPCLKENR/W0h

GPT_A1_SLP_CLK_ENABLE

0h = Disable the GPT_A1 clock during sleep

1h = Enable the GPT_A1 clock during sleep

7-1NU2R0h
0RUNCLKENR/W0h

GPT_A1_RUN_CLK_ENABLE

0h = Disable the GPT_A1 clock during run

1h = Enable the GPT_A1 clock during run

15.6.33 GPT1SWRST Register (offset = 9Ch) [reset = 0h]

GPT1SWRST is shown in Figure 15-35 and described in Table 15-36.

Figure 15-35 GPT1SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-36 GPT1SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

GPT_A1_ENABLED_STATUS

0h = GPT_A1 clocks and resets are disabled

1h = GPT_A1 clocks and resets are enabled

0SWRSTR/W0h

GPT_A1_SOFT_RESET

0h = Deassert the soft reset for GPT_A1

1h = Assert the soft reset for GPT_A1

15.6.34 GPT2CLKEN Register (offset = A0h) [reset = 0h]

GPT2CLKEN is shown in Figure 15-36 and described in Table 15-37.

Figure 15-36 GPT2CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-37 GPT2CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

GPT_A2_DSLP_CLK_ENABLE

0h = Disable the GPT_A2 clock during deep-sleep

1h = Enable the GPT_A2 clock during deep-sleep

15-9NU1R0h
8SLPCLKENR/W0h

GPT_A2_SLP_CLK_ENABLE

0h = Disable the GPT_A2 clock during sleep

1h = Enable the GPT_A2 clock during sleep

7-1NU2R0h
0RUNCLKENR/W0h

GPT_A2_RUN_CLK_ENABLE

0h = Disable the GPT_A2 clock during run

1h = Enable the GPT_A2 clock during run

15.6.35 GPT2SWRST Register (offset = A4h) [reset = 0h]

GPT2SWRST is shown in Figure 15-37 and described in Table 15-38.

Figure 15-37 GPT2SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-38 GPT2SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

GPT_A2_ENABLED_STATUS

0h = GPT_A2 clocks and resets are disabled

1h = GPT_A2 clocks and resets are enabled

0SWRSTR/W0h

GPT_A2_SOFT_RESET

0h = Deassert the soft reset for GPT_A2

1h = Assert the soft reset for GPT_A2

15.6.36 GPT3CLKEN Register (offset = A8h) [reset = 0h]

GPT3CLKEN is shown in Figure 15-38 and described in Table 15-39.

Figure 15-38 GPT3CLKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-39 GPT3CLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

GPT_A3_DSLP_CLK_ENABLE

0h = Disable the GPT_A3 clock during deep-sleep

1h = Enable the GPT_A3 clock during deep-sleep

15-9NU1R0h
8SLPCLKENR/W0h

GPT_A3_SLP_CLK_ENABLE

0h = Disable the GPT_A3 clock during sleep

1h = Enable the GPT_A3 clock during sleep

7-1NU2R0h
0RUNCLKENR/W0h

GPT_A3_RUN_CLK_ENABLE

0h = Disable the GPT_A3 clock during run

1h = Enable the GPT_A3 clock during run

15.6.37 GPT3SWRST Register (offset = ACh) [reset = 0h]

GPT3SWRST is shown in Figure 15-39 and described in Table 15-40.

Figure 15-39 GPT3SWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-40 GPT3SWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

GPT_A3_ENABLED_STATUS

0h = GPT_A3 clocks and resets are disabled

1h = GPT_A3 clocks and resets are enabled

0SWRSTR/W0h

GPT_A3_SOFT_RESET

0h = Deassert the soft reset for GPT_A3

1h = Assert the soft reset for GPT_A3

15.6.38 MCASPCLKCFG0 Register (offset = B0h) [reset = A0000h]

MCASPCLKCFG0 is shown in Figure 15-40 and described in Table 15-41.

Figure 15-40 MCASPCLKCFG0 Register
31302928272625242322212019181716
RESERVEDDIVISR
R-0hR/W-Ah
1514131211109876543210
FRACTN
R/W-0h
Table 15-41 MCASPCLKCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0h
25-16DIVISRR/WAh

MCASP_FRAC_DIV_DIVISOR. If the root clock frequency is Fref and the required output clock frequency is Freq, the ratio of these two frequencies (Fref/Freq) can be represented as = I.F where I is the integer part of the ratio and F is the fractional part of the ratio.

15-0FRACTNR/W0h

MCASP_FRAC_DIV_FRACTION. If the root clock frequency is Fref and the required output clock frequency is Freq, the ratio of these two frequencies (Fref/Freq) can be represented as = I.F where I is the integer part of the ratio and F is the fractional part of the ratio.

15.6.39 MCASPCLKCFG1 Register (offset = B4h) [reset = 0h]

MCASPCLKCFG1 is shown in Figure 15-41 and described in Table 15-42.

Figure 15-41 MCASPCLKCFG1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDIVIDRSWRST
R-0hR/W-0h
15141312111098
RESERVEDSPARE
R-0hR/W-0h
76543210
SPARE
R/W-0h
Table 15-42 MCASPCLKCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DIVIDRSWRSTR/W0h

MCASP_FRAC_DIV_SOFT_RESET

0h = Do not assert the reset for MCASP frac clk-div

1h = Assert the reset for MCASP Frac-clk div

15-10RESERVEDR0h
9-0SPARER/W0h

MCASP_FRAC_DIV_PERIOD. This bit field is not used in hardware. Can be used as a spare RW register.

15.6.40 I2CLCKEN Register (offset = D8h) [reset = 0h]

I2CLCKEN is shown in Figure 15-42 and described in Table 15-43.

Figure 15-42 I2CLCKEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDSLPCLKEN
R-0hR/W-0h
15141312111098
NU1SLPCLKEN
R-0hR/W-0h
76543210
NU2RUNCLKEN
R-0hR/W-0h
Table 15-43 I2CLCKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16DSLPCLKENR/W0h

I2C_DSLP_CLK_ENABLE

0h = Disable the I2C clock during deep-sleep

1h = Enable the I2C clock during deep-sleep

15-9NU1R0h
8SLPCLKENR/W0h

I2C_SLP_CLK_ENABLE

0h = Disable the I2C clock during sleep

1h = Enable the I2C clock during sleep

7-1NU2R0h
0RUNCLKENR/W0h

I2C_RUN_CLK_ENABLE

0h = Disable the I2C clock during run

1h = Enable the I2C clock during run

15.6.41 I2CSWRST Register (offset = DCh) [reset = 0h]

I2CSWRST is shown in Figure 15-43 and described in Table 15-44.

Figure 15-43 I2CSWRST Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENSTSSWRST
R-0hR-0hR/W-0h
Table 15-44 I2CSWRST Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1ENSTSR0h

I2C_ENABLED_STATUS

0h = I2C clocks and resets are disabled

1h = I2C clocks and resets are enabled

0SWRSTR/W0h

I2C_SOFT_RESET

0h = Deassert the soft reset for Shared-I2C

1h = Assert the soft reset for Shared-I2C

15.6.42 LPDSREQ Register (offset = E4h) [reset = 0h]

LPDSREQ is shown in Figure 15-44 and described in Table 15-45.

Figure 15-44 LPDSREQ Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLPDSREQ
R-0hR/W-0h
Table 15-45 LPDSREQ Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0LPDSREQR/W0h

APPS_LPDS_REQ

1h = Request for LPDS

15.6.43 TURBOREQ Register (offset = ECh) [reset = 0h]

TURBOREQ is shown in Figure 15-45 and described in Table 15-46.

Figure 15-45 TURBOREQ Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTURBOREQ
R-0hR/W-0h
Table 15-46 TURBOREQ Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TURBOREQR/W0h

APPS_TURBO_REQ

1h = Request for TURBO

15.6.44 DSLPWAKECFG Register (offset = 108h) [reset = 0h]

DSLPWAKECFG is shown in Figure 15-46 and described in Table 15-47.

Figure 15-46 DSLPWAKECFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEXITDSLPBYNWPENEXITDSLPBYTMREN
R-0hR/W-0hR/W-0h
Table 15-47 DSLPWAKECFG Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1EXITDSLPBYNWPENR/W0h

DSLP_WAKE_FROM_NWP_ENABLE

0h = Disable NWP to wake APPS from deep-sleep

1h = Enable the NWP to wake APPS from deep-sleep

0EXITDSLPBYTMRENR/W0h

DSLP_WAKE_TIMER_ENABLE

0h = Disable deep-sleep wake timer in APPS RCM

1h = Enable deep-sleep wake timer in APPS RCM for deep-sleep

15.6.45 DSLPTIMRCFG Register (offset = 10Ch) [reset = 0h]

DSLPTIMRCFG is shown in Figure 15-47 and described in Table 15-48.

Figure 15-47 DSLPTIMRCFG Register
313029282726252423222120191817161514131211109876543210
TIMROPPCFGTIMRCFG
R/W-0hR/W-0h
Table 15-48 DSLPTIMRCFG Register Field Descriptions
BitFieldTypeResetDescription
31-16TIMROPPCFGR/W0h

DSLP_WAKE_TIMER_OPP_CFG Configuration (in slow_clks) which indicates when to request for OPP during deep-sleep exit

15-0TIMRCFGR/W0h

DSLP_WAKE_TIMER_WAKE_CFG Configuration (in slow_clks) which indicates when to request for WAKE during deep-sleep exit

15.6.46 SLPWAKEEN Register (offset = 110h) [reset = 0h]

SLPWAKEEN is shown in Figure 15-48 and described in Table 15-49.

Figure 15-48 SLPWAKEEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEITBYNWPEXITBYTIMR
R-0hR/W-0hR/W-0h
Table 15-49 SLPWAKEEN Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1EITBYNWPR/W0h

SLP_WAKE_FROM_NWP_ENABLE

0h = Disable the sleep wakeup due to NWP request

1h = Enable the sleep wakeup due to NWP request

0EXITBYTIMRR/W0h

SLP_WAKE_TIMER_ENABLE

0h = Disable the sleep wakeup due to sleep-timer

1h = Enable the sleep wakeup due to sleep-timer

15.6.47 SLPTMRCFG Register (offset = 114h) [reset = 0h]

SLPTMRCFG is shown in Figure 15-49 and described in Table 15-50.

Figure 15-49 SLPTMRCFG Register
313029282726252423222120191817161514131211109876543210
TMRCFG
R/W-0h
Table 15-50 SLPTMRCFG Register Field Descriptions
BitFieldTypeResetDescription
31-0TMRCFGR/W0h

SLP_WAKE_TIMER_CFG Configuration (number of sysclks-80MHz) for the Sleep wake-up timer.

15.6.48 WAKENWP Register (offset = 118h) [reset = 0h]

WAKENWP is shown in Figure 15-50 and described in Table 15-51.

Figure 15-50 WAKENWP Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDWAKENWP
R-0hR/W-0h
Table 15-51 WAKENWP Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0WAKENWPR/W0h

APPS_TO_NWP_WAKEUP_REQUEST. When 1 => APPS generated a wake request to NWP (When NWP is in any of its low-power modes: SLP/DSLP/LPDS)

15.6.49 RCM_IS Register (offset = 120h) [reset = 0h]

RCM_IS is shown in Figure 15-51 and described in Table 15-52.

Figure 15-51 RCM_IS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDWAKETIMRIRQRESERVEDPLLLOCKRESERVED
R-0hR-0hR-0hR-0hR-0h
76543210
RESERVEDEXITDSLPBYTMREXITSLPBYTMREXITDSLPBYNWPEXITSLPBYNWP
R-0hR-0hR-0hR-0hR-0h
Table 15-52 RCM_IS Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14WAKETIMRIRQR0h

To enable the RTC timer interrupt, set 0th bit of HIB3P3:MEM_HIB_RTC_IRQ_ENABLE(0x4402 F854) and 2nd bit of RCM_IEN(0x124) to 1,

1h = indicates interrupt to the APPS processor due to the RTC timer reaching the programmed value.

13RESERVEDR0h
12PLLLOCKR0h

Enable this interrupt by setting 0th bit of RCM_IEN(0x124).

1h = Indicates that an interrupt was received by the processor because of PLL lock.

11-4RESERVEDR0h
3EXITDSLPBYTMRR0h

apps_deep_sleep_timer_wake

1h = Indicates that deep-sleep timer expiry had caused the wakeup from deep-sleep.

2EXITSLPBYTMRR0h

apps_sleep_timer_wake

1h = Indicates that sleep timer expiry had caused the wakeup from sleep.

1EXITDSLPBYNWPR0h

apps_deep_sleep_wake_from_nwp

1h = Indicates that NWP had caused the wakeup from deep-sleep.

0EXITSLPBYNWPR0h

apps_sleep_wake_from_nwp

1h = Indicates that NWP had caused the wakeup from sleep

15.6.50 RCM_IEN Register (offset = 124h) [reset = 0h]

RCM_IEN is shown in Figure 15-52 and described in Table 15-53.

Figure 15-52 RCM_IEN Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDWAKETIMERIRQRESERVEDPLLLOCKIRQ
R-0hR/W-0hR-0hR/W-0h
Table 15-53 RCM_IEN Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2WAKETIMERIRQR/W0h

To enable RTC timer interrupt set 0th bit of HIB3P3:MEM_HIB_RTC_IRQ_ENABLE(0x4402 F854) to 1

0h = Unmask this interrupt.

1h = Unmask interrupt to the APPS processor when RTC timer reaches the programmed value.

1RESERVEDR0h
0PLLLOCKIRQR/W0h

0h = Mask this interrupt

1h = Unmask Interrupt to APPS processor when PLL is locked.