Reload Value

Value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0.

Current Value This field contains the current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register. Clearing this register also clears the COUNT bit of the STCTRL register.

Implementer Code

41h = ARM

Variant Number

0h = The rn value in the rnpn product revision identifier, for example, the 0 in r0p0.

Constant Value Description 0xF Always reads as 0xF.

Part Number

C24h = Cortex-M4 application processor in CC32xx.

Revision Number

1h = The pn value in the rnpn product revision identifier; for example, the 1 in r0p1.

NMI Set Pending

Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it registers the setting of this bit, and clears this bit on entering the interrupt handler. A read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.

0h (W) = On a write, no effect.

0h (R) = On a read, indicates an NMI exception is not pending.

1h (W) = On a write, changes the NMI exception state to pending.

1h (R) = On a read, indicates an NMI exception is pending.

PendSV Set Pending

Setting this bit is the only way to set the PendSV exception state to pending. This bit is cleared by writing a 1 to the UNPENDSV bit.

0h (W) = On a write, no effect.

0h (R) = On a read, indicates a PendSV exception is not pending.

1h (W) = On a write, changes the PendSV exception state to pending.

1h (R) = On a read, indicates a PendSV exception is pending.

PendSV Clear Pending

This bit is write onl on a register read, its value is unknown.

0h = On a write, no effect.

1h = On a write, removes the pending state from the PendSV exception.

SysTick Set Pending

This bit is cleared by writing a 1 to the PENDSTCLR bit.

0h (W) = On a write, no effect.

0h (R) = On a read, indicates a SysTick exception is not pending.

1h (W) = On a write, changes the SysTick exception state to pending.

1h (R) = On a read, indicates a SysTick exception is pending.

SysTick Clear Pending

This bit is write only on a register read, its value is unknown.

0h = On a write, no effect.

1h = On a write, removes the pending state from the SysTick exception.

Debug Interrupt Handling

This bit is only meaningful in debug mode, and reads as zero when the processor is not in debug mode.

0h = The release from halt does not take an interrupt.

1h = The release from halt takes an interrupt.

Interrupt Pending

This bit provides status for all interrupts excluding NMI and faults.

0h = No interrupt is pending.

1h = An interrupt is pending.

Interrupt Pending Vector Number

This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.

0h = No exceptions are pending

1h = Reserved

2h = NMI

3h = Hard fault

4h = Memory management fault

5h = Bus fault

6h = Usage fault

7h- Ah = Reserved

Bh = SVCall

Ch = Reserved for Debug

Dh = Reserved

Eh = PendSV

Fh = SysTick

10h = Interrupt Vector 0

11h = Interrupt Vector 1

...

D9h = Interrupt Vector 199

Return to Base

This bit provides status for all interrupts excluding NMI and faults. This bit only has meaning if the processor is currently executing an ISR (the Interrupt Program Status (IPSR) register is non-zero).

0h = There are preempted active exceptions to execute.

1h = There are no active exceptions, or the currently executing exception is the only active exception.

Interrupt Pending Vector Number

This field contains the active exception number. The exception numbers can be found in the description for the VECPEND field. If this field is clear, the processor is in Thread mode.

This field contains the same value as the ISRNUM field in the IPSR register.

Subtract 16 from this value to obtain the IRQ number required to index into the Interrupt Set Enable (ENn), Interrupt Clear Enable (DISn), Interrupt Set Pending (PENDn), Interrupt Clear Pending (UNPENDn), and Interrupt Priority (PRIn) registers.

Vector Table Offset

When configuring the OFFSET field, the offset must be aligned to the number of exception entries in the vector table. Because there are 199 interrupts, the offset must be aligned on a 1024-byte boundary.

Register Key

This field is used to guard against accidental writes to this register. 0x05FA must be written to this field in order to change the bits in this register. On a read, 0xFA05 is returned.

Data Endianess

The CC32xx implementation uses only little-endian mode, so this is cleared to 0.

Interrupt Priority Grouping

This field determines the split of group priority from subpriority

System Reset Request

This bit is automatically cleared during the reset of the core and reads as 0.

0h = No effect.

1h = Resets the core and all on-chip peripherals except the Debug interface.

Clear Active NMI / Fault

This bit is reserved for debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable.

System Reset

This bit is reserved for debug use and reads as 0. This bit must be written as a 0, otherwise behavior is unpredictable.

Wake Up on Pending

0h = Only enabled interrupts or events can wake up the processor; disabled interrupts are excluded.

1h = Enabled events and all interrupts, including disabled interrupts, can wake up the processor.

Deep Sleep Enable

0h = Use Sleep mode as the low power mode.

1h = Use Deep-sleep mode as the low power mode.

Sleep on ISR Exit

Setting this bit enables an interrupt-driven application to avoid returning to an empty main application.

0h = When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode.

1h = When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR.

Stack Alignment on Exception Entry

On exception entry, the processor uses bit 9 of the stacked PSR to indicate the stack alignment. On return from the exception, it uses this stacked bit to restore the correct stack alignment.

0h = The stack is 4-byte aligned.

1h = The stack is 8-byte aligned.

Ignore Bus Fault in NMI and Fault

This bit enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. The setting of this bit applies to the hard fault, NMI, and FAULTMASK-escalated handlers. Set this bit only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe system devices and bridges to detect control path problems and fix them.

0h = Data bus faults caused by load and store instructions cause a lock-up.

1h = Handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.

Trap on Divide by 0

This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0.

0h = Do not trap on divide by 0. A divide by zero returns a quotient of 0.

1h = Trap on divide by 0.

Trap on Unaligned Access

Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of whether UNALIGNED is set.

0h = Do not trap on unaligned halfword and word accesses.

1h = Trap on unaligned halfword and word accesses. An unaligned access generates a usage fault.

Allow Main Interrupt Trigger

0h = Disables unprivileged software access to the SWTRIG register.

1h = Enables unprivileged software access to the SWTRIG register.

Thread State Control

0h = The processor can enter Thread mode only when no exception is active.

1h = The processor can enter Thread mode from any level under the control of an EXC_RETURN value.

Usage Fault Priority

This field configures the priority level of the usage fault. Configurable priority values are in the range 0-7, with lower values having higher priority.

Bus Fault Priority

This field configures the priority level of the bus fault. Configurable priority values are in the range 0-7, with lower values having higher priority.

Memory Management Fault Priority

This field configures the priority level of the memory management fault. Configurable priority values are in the range 0-7, with lower values having higher priority.

SVCall Priority

This field configures the priority level of SVCall. Configurable priority values are in the range 0-7, with lower values having higher priority.

SysTick Exception Priority

This field configures the priority level of the SysTick exception. Configurable priority values are in the range 0-7, with lower values having higher priority.

PendSV Priority

This field configures the priority level of PendSV. Configurable priority values are in the range 0-7, with lower values having higher priority.

Debug Priority

This field configures the priority level of Debug. Configurable priority values are in the range 0-7, with lower values having higher priority.

Usage Fault Enable

0h = Disables the usage fault exception.

1h = Enables the usage fault exception.

Bus Fault Enable

0h = Disables the bus fault exception.

1h = Enables the bus fault exception.

Memory Management Fault Enable

0h = Disables the memory management fault exception.

1h = Enables the memory management fault exception.

SVC Call Pending

This bit can be modified to change the pending status of the SVC call exception.

0h = An SVC call exception is not pending.

1h = An SVC call exception is pending.

Bus Fault Pending

This bit can be modified to change the pending status of the bus fault exception.

0h = A bus fault exception is not pending.

1h = A bus fault exception is pending.

Memory Management Fault Pending

This bit can be modified to change the pending status of the memory management fault exception.

0h = A memory management fault exception is not pending.

1h = A memory management fault exception is pending.

Usage Fault Pending

This bit can be modified to change the pending status of the usage fault exception.

0h = A usage fault exception is not pending.

1h = A usage fault exception is pending.

SysTick Exception Active

This bit can be modified to change the active status of the SysTick exception, however, see the Caution above before setting this bit.

0h = A SysTick exception is not active.

1h = A SysTick exception is active.

PendSV Exception Active

This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit.

0h = A PendSV exception is not active.

1h = A PendSV exception is active.

Debug Monitor Active

0h = The Debug monitor is not active.

1h = The Debug monitor is active.

SVC Call Active

This bit can be modified to change the active status of the SVC call exception, however, see the Caution above before setting this bit.

0h = SVC call is not active.

1h = SVC call is active.

Usage Fault Active

This bit can be modified to change the active status of the usage fault exception, however, see the Caution above before setting this bit.

0h = Usage fault is not active.

1h = Usage fault is active.

Bus Fault Active

This bit can be modified to change the active status of the bus fault exception, however, see the Caution above before setting this bit.

0h = Bus fault is not active.

1h = Bus fault is active.

Memory Management Fault Active

This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit.

0h = Memory management fault is not active.

1h = Memory management fault is active.

Divide-by-Zero Usage Fault

When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero. Trapping on divide-by-zero is enabled by setting the DIV0 bit in the Configuration and Control (CFGCTRL) register. This bit is cleared by writing a 1 to it.

0h = No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled.

1h = The processor has executed an SDIV or UDIV instruction with a divisor of 0.

Unaligned Access Usage Fault

Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the configuration of this bit. Trapping on unaligned access is enabled by setting the UNALIGNED bit in the CFGCTRL register. This bit is cleared by writing a 1 to it.

0h = No unaligned access fault has occurred, or unaligned access trapping is not enabled.

1h = The processor has made an unaligned memory access.

No Coprocessor Usage Fault

This bit is cleared by writing a 1 to it.

0h = A usage fault has not been caused by attempting to access a coprocessor.

1h = The processor has attempted to access a coprocessor.

Invalid PC Load Usage Fault

When this bit is set, the PC value stacked for the exception return points to the instruction that tried to perform the illegal load of the PC. This bit is cleared by writing a 1 to it.

0h = A usage fault has not been caused by attempting to load an invalid PC value.

1h = The processor has attempted an illegal load of EXC_RETURN to the PC as a result of an invalid context or an invalid EXC_RETURN value.

Invalid State Usage Fault

When this bit is set, the PC value stacked for the exception return points to the instruction that attempted the illegal use of the Execution Program Status Register (EPSR) register. This bit is not set if an undefined instruction uses the EPSR register. This bit is cleared by writing a 1 to it.

0h = A usage fault has not been caused by an invalid state.

1h = The processor has attempted to execute an instruction that makes illegal use of the EPSR register.

Undefined Instruction Usage Fault

When this bit is set, the PC value stacked for the exception return points to the undefined instruction. An undefined instruction is an instruction that the processor cannot decode. This bit is cleared by writing a 1 to it.

0h = A usage fault has not been caused by an undefined instruction.

1h = The processor has attempted to execute an undefined instruction.

Bus Fault Address Register Valid

This bit is set after a bus fault, where the address is known. Other faults can clear this bit, such as a memory management fault occurring later. If a bus fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active bus fault handler whose FAULTADDR register value has been overwritten. This bit is cleared by writing a 1 to it.

0h = The value in the Bus Fault Address (FAULTADDR) register is not a valid fault address.

1h = The FAULTADDR register is holding a valid fault address.

N/A

Stack Bus Fault

When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it.

0h = No bus fault has occurred on stacking for exception entry.

1h = Stacking for an exception entry has caused one or more bus faults.

Unstack Bus Fault

This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it.

0h = No bus fault has occurred on unstacking for a return from exception.

1h = Unstacking for a return from exception has caused one or more bus faults.

Imprecise Data Bus Error

When this bit is set, a fault address is not written to the FAULTADDR register. This fault is asynchronous. Therefore, if the fault is detected when the priority of the current process is higher than the bus fault priority, the bus fault becomes pending and becomes active only when the processor returns from all higher-priority processes. If a precise fault occurs before the processor enters the handler for the imprecise bus fault, the handler detects that both the IMPRE bit is set and one of the precise fault status bits is set. This bit is cleared by writing a 1 to it.

0h = An imprecise data bus error has not occurred.

1h = A data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error.

Precise Data Bus Error

When this bit is set, the fault address is written to the FAULTADDR register. This bit is cleared by writing a 1 to it.

0h = A precise data bus error has not occurred.

1h = A data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault.

Instruction Bus Error

The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register. This bit is cleared by writing a 1 to it.

0h = An instruction bus error has not occurred.

1h = An instruction bus error has occurred.

Memory Management Fault Address Register Valid

If a memory management fault occurs and is escalated to a hard fault because of priority, the hard fault handler must clear this bit. This action prevents problems if returning to a stacked active memory management fault handler whose MMADDR register value has been overwritten.

0h = The This bit is cleared by writing a 1 to it. value in the Memory Management Fault Address (MMADDR) register is not a valid fault address.

1h = The MMADDR register is holding a valid fault address.

N/A

Stack Access Violation

When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it.

0h = No memory management fault has occurred on stacking for exception entry.

1h = Stacking for an exception entry has caused one or more access violations.

Unstack Access Violation

This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present. The SP is not adjusted from the failing return, a new save is not performed, and a fault address is not written to the MMADDR register. This bit is cleared by writing a 1 to it.

0h = No memory management fault has occurred on unstacking for a return from exception.

1h = Unstacking for a return from exception has caused one or more access violations.

Data Access Violation

When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is written to the MMADDR register. This bit is cleared by writing a 1 to it.

0h = A data access violation has not occurred.

1h = The processor attempted a load or store at a location that does not permit the operation.

Instruction Access Violation

This fault occurs on any access to an XN region. When this bit is set, the PC value stacked for the exception return points to the faulting instruction and the address of the attempted access is not written to the MMADDR register. This bit is cleared by writing a 1 to it.

0h = An instruction access violation has not occurred.

1h = The processor attempted an instruction fetch from a location that does not permit execution.

Debug Event

This bit is reserved for debug use. This bit must be written as a 0, otherwise behavior is unpredictable.

Forced Hard Fault

When this bit is set, the hard fault handler must read the other fault status registers to find the cause of the fault. This bit is cleared by writing a 1 to it.

0h = No forced hard fault has occurred.

1h = A forced hard fault has been generated by escalation of a fault with configurable priority that cannot be handled, either because of priority or because it is disabled.

Vector Table Read Fault

This error is always handled by the hard fault handler. When this bit is set, the PC value stacked for the exception return points to the instruction that was preempted by the exception. This bit is cleared by writing a 1 to it.

0h = No bus fault has occurred on a vector table read.

1h = A bus fault occurred on a vector table read.

Fault Address

When the FAULTADDRV bit of BFAULTSTAT is set, this field holds the address of the location that generated the bus fault.

Interrupt ID

This field holds the interrupt ID of the required SGI. For example, a value of 0x3 generates an interrupt on IRQ3.