TIDUE53J March   2018  – February 2025 TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC5350
      3. 2.2.3  TMS320F28379D
      4. 2.2.4  AMC3306M05
      5. 2.2.5  OPA4388
      6. 2.2.6  TMCS1123
      7. 2.2.7  AMC0330R
      8. 2.2.8  AMC0381D
      9. 2.2.9  UCC14341
      10. 2.2.10 UCC33421
    3. 2.3 System Design Theory
      1. 2.3.1 Three-Phase T-Type Inverter
        1. 2.3.1.1 Architecture Overview
        2. 2.3.1.2 LCL Filter Design
        3. 2.3.1.3 Inductor Design
        4. 2.3.1.4 SiC MOSFETs Selection
        5. 2.3.1.5 Loss Estimations
      2. 2.3.2 Voltage Sensing
      3. 2.3.3 Current Sensing
      4. 2.3.4 System Auxiliary Power Supply
      5. 2.3.5 Gate Drivers
        1. 2.3.5.1 1200-V SiC MOSFETs
        2. 2.3.5.2 650-V SiC MOSFETs
        3. 2.3.5.3 Gate Driver Bias Supply
      6. 2.3.6 Control Design
        1. 2.3.6.1 Current Loop Design
        2. 2.3.6.2 PFC DC Bus Voltage Regulation Loop Design
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Test Hardware Required
        2. 3.1.1.2 Microcontroller Resources Used on the Design (TMS320F28379D)
        3. 3.1.1.3 F28377D, F28379D Control-Card Settings
        4. 3.1.1.4 Microcontroller Resources Used on the Design (TMS320F280039C)
      2. 3.1.2 Software
        1. 3.1.2.1 Getting Started With Firmware
          1. 3.1.2.1.1 Opening the CCS project
          2. 3.1.2.1.2 Digital Power SDK Software Architecture
          3. 3.1.2.1.3 Interrupts and Lab Structure
          4. 3.1.2.1.4 Building, Loading, and Debugging the Firmware
          5. 3.1.2.1.5 CPU Loading
        2. 3.1.2.2 Protection Scheme
        3. 3.1.2.3 PWM Switching Scheme
        4. 3.1.2.4 ADC Loading
    2. 3.2 Testing and Results
      1. 3.2.1 Lab 1
      2. 3.2.2 Testing Inverter Operation
        1. 3.2.2.1 Lab 2
        2. 3.2.2.2 Lab 3
        3. 3.2.2.3 Lab 4
      3. 3.2.3 Testing PFC Operation
        1. 3.2.3.1 Lab 5
        2. 3.2.3.2 Lab 6
        3. 3.2.3.3 Lab 7
      4. 3.2.4 Test Setup for Efficiency
      5. 3.2.5 Test Results
        1. 3.2.5.1 PFC Mode
          1. 3.2.5.1.1 PFC Start-Up – 230 VRMS, 400 VL-L AC Voltage
          2. 3.2.5.1.2 Steady State Results - PFC Mode
          3. 3.2.5.1.3 Efficiency, THD, and Power Factor Results, 60 Hz – PFC Mode
          4. 3.2.5.1.4 Transient Test With Step Load Change
        2. 3.2.5.2 Inverter Mode
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Trademarks
  12. 6About the Authors
  13. 7Revision History

3.2.3.2 Lab 6

The current loop for the PFC is checked in this build level. Lab 6 is primarily meant for tuning the current loop and optimizing performance. This lab can be safely started at low voltage and low power because starting at higher power without a supervisory voltage loop can boost the voltage due to overcurrent events and cause blown switches. Carefully set the TINV_idRef_pu variable so as to avoid overcurrent trips and high voltages at the DC terminals. Also the TINV_idRef_pu is defined with a negative sign for PFC mode of operation and with a positive sign for inverter mode of operation.

Figure 3-22 describes the software flow for running Lab 6.

TIDA-01606 Lab 6 Software Diagram Figure 3-22 Lab 6 Software Diagram

Set the project to Lab 6 by changing the lab number in the <tinv_settings.h> or main.syscfg file, (this is changed by powerSUITE GUI when using powerSUITE project)

In the user settings.h file some additional options are available, but the following are used for the tests documented in this design guide.

#if TINV_LAB == 6
#define TINV_TEST_SETUP TINV_TEST_SETUP_RES_LOAD
#define TINV_PROTECTION TINV_PROTECTION_ENABLED
#define TINV_SFRA_TYPE TINV_SFRA_CURRENT
#define TINV_SFRA_AMPLITUDE (float32_t)TINV_SFRA_INJECTION_AMPLITUDE_LEVEL2
#define TINV_POWERFLOW_MODE TINV_RECTIFIERER_MODE
#define TINV_DC_CHECK 0
#define TINV_SPLL_TYPE TINV_SPLL_SRF
#endif

In this check the software is run on the hardware, or the HIL platform, or both.

See the hardware test set up section for actual details of the equipment used for configuring the test. Do not supply any high-voltage power to the board yet.

  • First launch the main.syscfg and select Lab 6 in the project options. The compensator style (PI compensator) and the tuning loop (current loop) is automatically populated. Now click the run compensation designer icon and the compensation designer tool launches, with the model of the current loop plant with parameters specified on the powerSUITE page.
  • The current compensator coefficients used for running the control loop are shown in the following code. The user can modify these coefficients to meet the necessary loop bandwidth and phase margin. The ideal coefficients with resistive load are slightly different than the one used for grid connection because the grid impedance is very low. The compensator design transfer function and response are shown in Figure 3-23.
    #define TINV_GV_PI_KP ((float32_t) 1.9979056049)
#define TINV_GV_PI_KI ((float32_t) 0.0041887902)
    TIDA-01606 Compensator Design GUI - Current Loop PI Coefficients Figure 3-23 Compensator Design GUI - Current Loop PI Coefficients
  • Once satisfied with the proportional and integral gain values, click the Save COMP button. This saves the compensator values into the project. Close the Compensation Designer, and return to the powerSUITE page.
  • Turn on the auxiliary power supply, set at 12 V. Build and load the code, use the lab6.js file to populate the watch variables in the CCS window.
  • Set the e-load CV voltage to 100 V, 20 A limit.
  • Set the AC input voltage to 30 VRMS with appropriate current limit.
  • Make sure to enable the fans when testing at high power using TINV_fanSet function in the CCS watch window during the debug session.
  • After turning on the AC power supply, immediately turn on the relay by writing a 1 to TINV_neutralRelaySet. Make sure that the relay is turned on immediately (within 2 seconds) after turning on the AC supply.
  • Set TINV_idRef_pu to –0.015 pu
  • To start the PFC mode, enter "1" on the TINV_startPowerStage variable, the current is now drawn from the grid as a sinusoidal signal (with some harmonics as the current is at low power) and boost the action seen on the vBus. The output voltage boosts from 75 V to around 100 V.
  • The current becomes sinusoidal as the load is increased. This verifies start-up of PFC at 30 VRMS.
  • Next, redo the PFC tests with 120 VRMS and 230 VRMSinputs.
  • Set the e-load CV voltage to 800 V, 20 A limit. Start the PFC boost similar to previously done.
    Note: Lab 7 introduces a voltage loop for the PFC.

    This lab relies on the e-load that regulates the output voltage. TINV_VBUS_OVERVOLT_LIMIT must be configured for these tests.

  • Figure 3-24 shows an example PFC closed current loop operating at 120 VRMS, 90 kHz PWM.
    TIDA-01606 PFC Current Loop Operating at 120 VRMS
    Scope signals: Channel 1 - DC voltage (blue), Channel 4- AC voltage ( green),
    Channel 3 - AC current (red). The voltage probes are scaled down at 500:1.
    Figure 3-24 PFC Current Loop Operating at 120 VRMS
  • Now repeat the previous steps to verify PFC at 220 VRMS.
  • Figure 3-25 shows an example PFC closed current loop operating at 230 VRMS, 90 kHz PWM.
    TIDA-01606 PFC Current Loop Operating at 230 VRMS, 90 kHz
    Scope signals: Channel 1 - DC voltage (blue), Channel 4- AC voltage ( green),
    Channel 3 - AC current (red). The voltage probes are scaled down at 500:1.
    Figure 3-25 PFC Current Loop Operating at 230 VRMS, 90 kHz
  • Figure 3-26 shows an example PFC closed current loop operating at 230 VRMS, 70 kHz PWM.
    TIDA-01606 PFC Current Loop Operating at 230 VRMS, 70 kHz
    Scope signals Scope signals: Channel 1 - DC voltage (blue), Channel 4- AC voltage ( green),
    Channel 3 - AC current (red). The voltage probes are scaled down at 500:1.
    Figure 3-26 PFC Current Loop Operating at 230 VRMS, 70 kHz
  • A soft start scheme is implemented at the start-up to make sure overcurrents are reduced at start-up. For this, the duty is restricted to the PWM module by adjusting the dead band set. Figure 3-27 shows the PWM configuration for this setup where the dead band is set to a large value and slowly reduced to the nominal value to limit the current spikes.
    TIDA-01606 Dead Band Soft Start PWM Configuration Figure 3-27 Dead Band Soft Start PWM Configuration
  • Figure 3-28 shows the effect of the start-up scheme without dead band implemented at start-up. Without soft start, a huge current spike appears which causes over current trip and the DC bus voltage also collapses. Figure 3-28 shows overcurrent without soft-start implementation.
    TIDA-01606 Without Soft Start
    Scope signals: Channel 1 - AC voltage (blue), Channel 2 - AC current (light green),
    Channel 3 - DC voltage (dark green)
    Figure 3-28 Without Soft Start

    Figure 3-29 shows reduced current spike with soft-start implementation.

    TIDA-01606 Soft Start With Adaptive Dead Band
    Scope signals: Channel 1 - AC voltage (blue), Channel 2 - AC current (light green),
    Channel 3 - DC voltage (dark green).
    Figure 3-29 Soft Start With Adaptive Dead Band
  • SFRA is integrated in the software of this lab to verify the designed compensator provides enough gain and phase margin by measuring on hardware. To run the SFRA, keep the project running and from the cfg page, click on the SFRA icon. The SFRA GUI pops up.
  • Select the options for the device on the SFRA GUI. For example, for F28377D, select floating point. Click on Setup Connection. On the pop-up window uncheck the boot on connect option, and select an appropriate COM port. Click the OK button. Return to the SFRA GUI, and click Connect.
  • The SFRA GUI connects to the device. An SFRA sweep can now be started by clicking the Start Sweep button. The complete SFRA sweep takes a few minutes to finish. Activity can be monitored by observing the progress bar on the SFRA GUI and also by checking the flashing blue LED on the back of the control card that indicates UART activity. Once complete, a graph with the open loop plot appears, as in Figure 3-30 and Figure 3-31 which corresponds to plant and loop response measured by the SFRA GUI respectively. This verifies that the designed compensator is indeed stable.
    TIDA-01606 PFC SFRA Plant Response for Current Loop Figure 3-30 PFC SFRA Plant Response for Current Loop
    TIDA-01606 PFC SFRA Loop Response for Current Loop Figure 3-31 PFC SFRA Loop Response for Current Loop
  • The frequency response data is also saved in the project folder under an SFRA data folder and is time stamped with the time of the SFRA run.
  • This completes verification of Lab 6.