TIDUE53J March   2018  – February 2025 TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC5350
      3. 2.2.3  TMS320F28379D
      4. 2.2.4  AMC3306M05
      5. 2.2.5  OPA4388
      6. 2.2.6  TMCS1123
      7. 2.2.7  AMC0330R
      8. 2.2.8  AMC0381D
      9. 2.2.9  UCC14341
      10. 2.2.10 UCC33421
    3. 2.3 System Design Theory
      1. 2.3.1 Three-Phase T-Type Inverter
        1. 2.3.1.1 Architecture Overview
        2. 2.3.1.2 LCL Filter Design
        3. 2.3.1.3 Inductor Design
        4. 2.3.1.4 SiC MOSFETs Selection
        5. 2.3.1.5 Loss Estimations
      2. 2.3.2 Voltage Sensing
      3. 2.3.3 Current Sensing
      4. 2.3.4 System Auxiliary Power Supply
      5. 2.3.5 Gate Drivers
        1. 2.3.5.1 1200-V SiC MOSFETs
        2. 2.3.5.2 650-V SiC MOSFETs
        3. 2.3.5.3 Gate Driver Bias Supply
      6. 2.3.6 Control Design
        1. 2.3.6.1 Current Loop Design
        2. 2.3.6.2 PFC DC Bus Voltage Regulation Loop Design
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Test Hardware Required
        2. 3.1.1.2 Microcontroller Resources Used on the Design (TMS320F28379D)
        3. 3.1.1.3 F28377D, F28379D Control-Card Settings
        4. 3.1.1.4 Microcontroller Resources Used on the Design (TMS320F280039C)
      2. 3.1.2 Software
        1. 3.1.2.1 Getting Started With Firmware
          1. 3.1.2.1.1 Opening the CCS project
          2. 3.1.2.1.2 Digital Power SDK Software Architecture
          3. 3.1.2.1.3 Interrupts and Lab Structure
          4. 3.1.2.1.4 Building, Loading, and Debugging the Firmware
          5. 3.1.2.1.5 CPU Loading
        2. 3.1.2.2 Protection Scheme
        3. 3.1.2.3 PWM Switching Scheme
        4. 3.1.2.4 ADC Loading
    2. 3.2 Testing and Results
      1. 3.2.1 Lab 1
      2. 3.2.2 Testing Inverter Operation
        1. 3.2.2.1 Lab 2
        2. 3.2.2.2 Lab 3
        3. 3.2.2.3 Lab 4
      3. 3.2.3 Testing PFC Operation
        1. 3.2.3.1 Lab 5
        2. 3.2.3.2 Lab 6
        3. 3.2.3.3 Lab 7
      4. 3.2.4 Test Setup for Efficiency
      5. 3.2.5 Test Results
        1. 3.2.5.1 PFC Mode
          1. 3.2.5.1.1 PFC Start-Up – 230 VRMS, 400 VL-L AC Voltage
          2. 3.2.5.1.2 Steady State Results - PFC Mode
          3. 3.2.5.1.3 Efficiency, THD, and Power Factor Results, 60 Hz – PFC Mode
          4. 3.2.5.1.4 Transient Test With Step Load Change
        2. 3.2.5.2 Inverter Mode
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Trademarks
  12. 6About the Authors
  13. 7Revision History

3.2.2 Testing Inverter Operation

Lab 2, Lab 3, and Lab 4 elaborate the steps for running the power stage in the inverter mode. Lab 2 is the inverter mode of operation in open loop. Lab 3 is the inverter mode of operation with closed current loop. Lab 4 is the grid connected inverter mode of operation and this is checked only under hardware-in-the-loop (HIL) platform and not on the hardware. The high voltage (800 VDC) is applied across terminals J13 and J18. 12-V auxiliary power supply is connected to terminal J3. Three-phase star connected resistive load is connected across terminals J14, J16, and J17. J30 is the protective earth terminal which is connected to the high-voltage power source earth.

A check for DC bus overvoltage is added to all Inverter Labs, Lab 1 through Lab 5, using a filtered value for the DC bus voltage. The TINV_filterAndCheckForBusOverVoltage() function runs from ISR1 and checks for DC bus overvoltage condition. Under overvoltage condition, this function shuts off all PWM outputs and registers the system operating state as bus overvoltage state. Filtered DC bus voltage is calculated from instantaneous sensed DC bus voltage using the averaging function EMAVG. This is all calculated inside ISR1. The user can set the TINV_VBUS_OVERVOLT_LIMIT in tinv_user_settings.h:

#define TINV_UNDERVOLT_LIMIT
#define TINV_VBUS_OVERVOLT_LIMIT 900
#define TINV_VBUS_CLAMP_MIN_PU 0.1f
#define TINV_GRID_OVER_UNDER_FREQ_LIMIT 3
#define TINV_GRID_OVER_UNDER_VRMS_LIMIT 35
#define TINV_UNIVERSAL_GRID_MAX_VRMS    240
#define TINV_UNIVERSAL_GRID_MIN_VRMS    20
#define TINV_UNIVERSAL_GRID_MAX_FREQ    65
#define TINV_UNIVERSAL_GRID_MIN_FREQ    45

The feed-forward and decoupling function is implemented inside ISR1 and added for all Inverter Labs that use a current loop. Therefore, for the inverter mode, this is done (feed-forward and decoupling) in Lab 3 and Lab 4. For this feed-forward and decoupling function, filtered DC bus voltage is compared against a user-defined minimum bus voltage to calculate a clamped filtered DC bus voltage. This is also done inside ISR1. This clamped filtered DC bus voltage and the current controller output are finally used to implement the feed-forward and decoupling function.

For SDFM-based current sensing, overcurrent protection (OCP) is also added for all Inverter Labs.