TIDUE53J March   2018  – February 2025 TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC5350
      3. 2.2.3  TMS320F28379D
      4. 2.2.4  AMC3306M05
      5. 2.2.5  OPA4388
      6. 2.2.6  TMCS1123
      7. 2.2.7  AMC0330R
      8. 2.2.8  AMC0381D
      9. 2.2.9  UCC14341
      10. 2.2.10 UCC33421
    3. 2.3 System Design Theory
      1. 2.3.1 Three-Phase T-Type Inverter
        1. 2.3.1.1 Architecture Overview
        2. 2.3.1.2 LCL Filter Design
        3. 2.3.1.3 Inductor Design
        4. 2.3.1.4 SiC MOSFETs Selection
        5. 2.3.1.5 Loss Estimations
      2. 2.3.2 Voltage Sensing
      3. 2.3.3 Current Sensing
      4. 2.3.4 System Auxiliary Power Supply
      5. 2.3.5 Gate Drivers
        1. 2.3.5.1 1200-V SiC MOSFETs
        2. 2.3.5.2 650-V SiC MOSFETs
        3. 2.3.5.3 Gate Driver Bias Supply
      6. 2.3.6 Control Design
        1. 2.3.6.1 Current Loop Design
        2. 2.3.6.2 PFC DC Bus Voltage Regulation Loop Design
  9. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Test Hardware Required
        2. 3.1.1.2 Microcontroller Resources Used on the Design (TMS320F28379D)
        3. 3.1.1.3 F28377D, F28379D Control-Card Settings
        4. 3.1.1.4 Microcontroller Resources Used on the Design (TMS320F280039C)
      2. 3.1.2 Software
        1. 3.1.2.1 Getting Started With Firmware
          1. 3.1.2.1.1 Opening the CCS project
          2. 3.1.2.1.2 Digital Power SDK Software Architecture
          3. 3.1.2.1.3 Interrupts and Lab Structure
          4. 3.1.2.1.4 Building, Loading, and Debugging the Firmware
          5. 3.1.2.1.5 CPU Loading
        2. 3.1.2.2 Protection Scheme
        3. 3.1.2.3 PWM Switching Scheme
        4. 3.1.2.4 ADC Loading
    2. 3.2 Testing and Results
      1. 3.2.1 Lab 1
      2. 3.2.2 Testing Inverter Operation
        1. 3.2.2.1 Lab 2
        2. 3.2.2.2 Lab 3
        3. 3.2.2.3 Lab 4
      3. 3.2.3 Testing PFC Operation
        1. 3.2.3.1 Lab 5
        2. 3.2.3.2 Lab 6
        3. 3.2.3.3 Lab 7
      4. 3.2.4 Test Setup for Efficiency
      5. 3.2.5 Test Results
        1. 3.2.5.1 PFC Mode
          1. 3.2.5.1.1 PFC Start-Up – 230 VRMS, 400 VL-L AC Voltage
          2. 3.2.5.1.2 Steady State Results - PFC Mode
          3. 3.2.5.1.3 Efficiency, THD, and Power Factor Results, 60 Hz – PFC Mode
          4. 3.2.5.1.4 Transient Test With Step Load Change
        2. 3.2.5.2 Inverter Mode
  10. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  11. 5Trademarks
  12. 6About the Authors
  13. 7Revision History

3.2.3.1 Lab 5

This is the first PFC lab. In this lab sensing is checked and no switching action occurs until clearPWMTrip is set to 1.

The hardware setup for the PFC mode is explained in Figure 3-17. TI recommends starting the PFC at a low voltage like 30 VRMS and connecting a 2-kΩ resistor.

Set the project to Lab 5 by changing the Lab Number in the <tinv_settings.h> or main.syscfg file, (this is changed with the powerSUITE GUI when using the powerSUITE project).

Under this condition, the converter operates as a rectifier and rectified current can be observed being drawn without any power factor correction. Software Phase-Lock Loop (SPLL) locking can also be safely verified in this build.

TIDA-01606 Lab 5 Software DiagramFigure 3-18 Lab 5 Software Diagram

Hence, the following variables are put on the data logger:

TINV_dVal1 = TINV_vGrid_A_sensed_pu;
TINV_dVal2 = TINV_angleSPLL_radians / (float32_t)(2.0f * TINV_PI);
TINV_dVal3 = TINV_vGrid_A_sensed_pu;
TINV_dVal4 = TINV_iInv_A_sensed_pu;
DLOG_4CH_run(&TINV_dLog1);

Make sure the grid frequency is specified correctly, the grid frequency can be changed through the sysconfig page for powerSUITE-based projects. If not using a powerSUITE-based project, modify the tinv_settings.h file. 

#define TINV_AC_FREQ_HZ ((float32_t)50)

Build and load the code, use the lab5.js file to populate the watch variables in the CCS window.

PLL lock can be checked by plotting the buffers. Use the graph1.graphprop to see the buffer through Tools → Graph → Dual Time.

Cosine transforms are used; therefore, the angle is 0 when Vgrid peaks.

Close the relay by writing a 1 to TINV_neutralRelaySet.

Initially, only run this test with 30 VRMS for safety, hence safely ramp the AC supply to 30 VRMS and observe the graph in the CCS debug window to confirm the PLL is locking. Figure 3-19 shows the low-voltage phase-locked loop check from watch window.

TIDA-01606 PLL - Grid Voltage SynchronizationFigure 3-19 PLL - Grid Voltage Synchronization

If the PLL is not locking, issue a tinv_reset_PLL command by setting the command to "1", which initiates a task to zero out an integrated error in the module and zero all the memory elements.

Similarly, the current flowing from the grid across all phases can be checked, using the graph watch window of CCS. Figure 3-20 shows the sensed grid currents from graph windowCheck for three phase grid currents observed from the watch window.

TIDA-01606 Sensed Grid Currents - PFC ModeFigure 3-20 Sensed Grid Currents - PFC Mode

To verify boost action in Lab 5, follow the steps according to the sequence provided:

  • Turn on the auxiliary power supply, set at 12 V and then debug and run the code.
  • Connect an acceptable load to the J13 and J18 terminals. Make sure to use a high load resistance (around 2 kΩ) which otherwise can lead to high inrush currents triggering the overcurrent flag. The e-load can also be used in constant voltage (CV) mode. Set the clamp voltage higher than 2.6 × the input AC phase voltage. For example, if 30 VRMS AC voltage is used, set the e-load CV voltage to at least 78 V (higher than the unboosted rectified voltage at the DC link).
  • Make sure to enable the fans when testing at high power using the TINV_fanSet function in the CCS watch window during the debug session.
  • Apply 30 VRMS AC voltage to the three phase terminals.
  • Immediately turn on the relay by writing a 1 to TINV_neutralRelaySet. Voltage starts to appear across the DC terminals.
  • Clear the PWM trip by setting TINV_clearPwmTrip to 1 to see a slight boost in DC voltage.

Before PFC action begins, a rectified current is drawn due to the load on the Vbus. As soon as clearPWMTrip is set to 1, a slight boost in DC voltage is evident.

Note:

There can be a situation in the labs for PFC (Lab 5, Lab 6, and Lab 7) where the converter operates as a rectifier and rectified current is seen being drawn without any power factor correction. But as soon as TINV_clearPwmTrip is set to 1, there is no switching action – the Gate Signals remain off.

This is because there is an overcurrent or DSAT flag (InvA_overcurrent, InvB_overcurrent,DSATA, DSATB) which is set in one of the three phases and this happens under three circumstances:

  1. On closing the relays, there is an inrush current which creates an overcurrent trip in one of the three phases.
  2. When TINV_clearPwmTrip is set to 1, the switching action causes one of the flags to be set.
  3. Setting TINV_StartpowerStage to 1 for closing the current and voltage loop.

The EPWM TZFLG is set to 0X000C and under this condition no switching occurs. So make sure the load resistance is increased so that the inrush currents do not cause a trip condition and the EPWM TZFLG changes from 0x0004 to 0x0000 and switching occurs.

Once the FLG is set to 0x000C, even if a TINV_reset_fault_status is performed to reset the faults and even though the faults are cleared, PWM action is not observed.

The goal is, as soon as the auxiliary power supply is started and the code debugged, all the faults – namely InvA_overcurrent, InvB_overcurrent, DSATA, DSATB; and so forth – are supposed to be set to zero so that the controller does not go into a trip state.

If possible, limit the slew rate on the AC source to 100 V/μs. This helps with the inrush current tripping the AC source OCP. This can happen if when the relay is left open for a long time causing the voltage on the EMI filter caps to decay close to 0 V, as shown in Figure 3-21. Later when the relay is closed, a large inrush current is in the reactive load which can trip the AC source OCP feature.

TIDA-01606 Inrush Current Due to Reactive Load Voltage Decay Following Precharge Period
Scope signals: Channel 1 - VL-L at input (blue), Channel 4 - voltage across EMI cap C68 VSN (light green),
Channel 3 - AC input current (red). The voltage probes are scaled down at 500:1.
Figure 3-21 Inrush Current Due to Reactive Load Voltage Decay Following Precharge Period