ADC32RF83

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Dual-channel, 14-bit, 3-GSPS, single DDC/channel, RF-sampling wideband receiver and feedback IC

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Product details

Parameters

Number of input channels 2 Resolution (Bits) 14 Sample rate (Max) (MSPS) 3000 Features Decimating Filter, Ultra High Speed Analog input BW (MHz) 3200 SFDR (Typ) (dB) 66 SNR (Typ) (dB) 61.1 Power consumption (Typ) (mW) 6400 Logic voltage DV/DD (Max) (V) 1.2 Logic voltage DV/DD (Min) (V) 1.1 Analog voltage AVDD (Max) (V) 1.25, 2 Analog voltage AVDD (Min) (V) 1.1, 1.8 Operating temperature range (C) -40 to 85 open-in-new Find other Receivers

Package | Pins | Size

VQFNP (RMP) 72 100 mm² 10 x 10 open-in-new Find other Receivers

Features

  • 14-Bit, Dual-Channel, 3-GSPS ADC
  • Noise Floor: –155 dBFS/Hz
  • RF Input Supports Up to 4.0 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 900 MHz, –2 dBFS):
    • SNR: 60.1 dBFS
    • SFDR: 66-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 67-dBc HD2, HD3
    • SFDR: 76-dBc Worst Spur
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel at 12.5 Gbps
  • Power Dissipation: 3.2 W/Ch at 3.0 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)
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Description

The ADC32RF8x (ADC32RF80 and ADC32RF83) is a 14-bit, 3-GSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF8x family delivers a noise spectral density of –155 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF8x supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 6
Type Title Date
* Datasheet ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices datasheet (Rev. A) Dec. 15, 2016
Application note Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) Sep. 05, 2017
Technical articles Why should you care about the noise immunity of MLVDS drivers and receivers? Jul. 26, 2017
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016
Technical articles RF sampling: analog-to-digital converter linearity sets sensitivity Sep. 29, 2016
Technical articles RF sampling: linearity performance is not so straightforward Aug. 30, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
Description

The ADC32RF80 evaluation module (EVM) demonstrates the performance of a dual 3-GSPS 14-bit analog-to-digital converter (ADC) with the JESD204B interface. The EVM includes the ADC32RF80 device, and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary (...)

Features
  • Onboard clock generation, or external clocking supported with LMK04828 generating SYSREF
  • JESD204B data interface to simplify digital interface; compliant up to 10.8-Gbps lane rates
  • Supports JESD204B subclass 1 for synchronization and compatibility
  • Optional decimation filter outputs sample data at (...)

Design tools & simulation

SIMULATION MODEL Download
SBAM273.ZIP (46 KB) - IBIS Model
SIMULATION MODEL Download
SBAM274.ZIP (3109 KB) - IBIS-AMI Model
CALCULATION TOOL Download
RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator
FREQ-DDC-FILTER-CALC This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of both (...)

Features
  • Frequency planning
  • Analog filtering
  • Decimation filter spur location

CAD/CAE symbols

Package Pins Download
VQFN (RMP) 72 View options
VQFN (RRH) 72 View options

Ordering & quality

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