ADC12DJ2700

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12-bit, dual 2.7-GSPS or single 5.4-GSPS, RF-sampling analog-to-digital converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 2700, 5400 Resolution (Bits) 12 Number of input channels 2, 1 Interface type JESD204B Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 2700 Architecture Folding Interpolating SNR (dB) 57.7 ENOB (Bits) 9 SFDR (dB) 75 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

FCBGA (AAV) 144 100 mm² 10 x 10 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • ADC core:
    • 12-bit resolution
    • Up to 5.4 GSPS in single-channel mode
    • Up to 2.7 GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (no signal, VFS = 1.0 VPP-DIFF):
      • Dual-channel mode: –151.6 dBFS/Hz
      • Single-channel mode: –153.8 dBFS/Hz
    • HD2, HD3: –65 dBc up to 3 GHz
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
    • Analog input common-mode (VICM): 0 V
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B serial data interface:
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
    • Four independent 32-Bit NCOs per DDC
  • Power consumption: 2.7 W
  • Power supplies: 1.1 V, 1.9 V

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open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADC12DJ2700 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ2700 can sample up to 2700 MSPS and up to 5400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ2700 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

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Type Title Date
* Datasheet ADC12DJ2700 5.4-GSPS Single-Channel or 2.7-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) Feb. 21, 2019
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
Application notes Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design May 30, 2018
User guides ADCxxDJxx00 Evaluation Module User's Guide (Rev. A) Jan. 09, 2018
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Technical articles How to minimize filter loss when you drive an ADC Oct. 20, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

The ADC12DJ2700 evaluation module (EVM) allows for the evaluation of the ADC12DJ2700 device. ADC12DJ2700 is a low-power, 12-bit, dual-channel 2.7-GSPS or single-channel 5.4-GSPS, RF-sampling analog-to-digital converter (ADC) with a buffered analog input, integrated digital down converter with (...)

Features
  • Flexible transformer-coupled analog input to allow for a variety of sources and frequencies
  • Easy-to-use software GUI to configure ADC12DJ2700, LMX2582, and LMK04828 devices for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High-Speed Data Converter Pro (...)

Design tools & simulation

SIMULATION MODELS Download
SLVMC42.ZIP (36 KB) - IBIS Model
SIMULATION MODELS Download
SLVMC55.ZIP (5569 KB) - IBIS-AMI Model
SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
CALCULATION TOOLS Download
RF-Sampling Frequency Planner, Analog Filter, and DDC Excel™ Calculator
FREQ-DDC-FILTER-CALC This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of both (...)

Features
  • Frequency planning
  • Analog filtering
  • Decimation filter spur location

Reference designs

REFERENCE DESIGNS Download
Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
TIDA-01021 — High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems
TIDA-01022 — This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
(ZEG) 144 View options
FCBGA (AAV) 144 View options

Ordering & quality

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