SN65LVDS33

ACTIVE

Quad LVDS receiver with -4 to 5-V common-mode range

Product details

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal ECL, LVPECL, PECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 4 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal ECL, LVPECL, PECL Output signal LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • 400-Mbps Signaling Rate1 and 200-Mxfr/s Data Transfer Rate
  • Operates With a Single 3.3-V Supply
  • –4-V to 5-V Common-Mode Input Voltage Range
  • Differential Input Thresholds <±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range
  • Integrated 110- Line Termination Resistors On LVDT Products
  • TSSOP Packaging (33 Only)
  • Complies With TIA/EIA-644 (LVDS)
  • Active Failsafe Assures a High-Level Output With No Input
  • Bus-Pin ESD Protection Exceeds 15 kV HBM
  • Input Remains High-Impedance on Power Down
  • TTL Inputs Are 5-V Tolerant
  • Pin-Compatible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B

1 The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

  • 400-Mbps Signaling Rate1 and 200-Mxfr/s Data Transfer Rate
  • Operates With a Single 3.3-V Supply
  • –4-V to 5-V Common-Mode Input Voltage Range
  • Differential Input Thresholds <±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range
  • Integrated 110- Line Termination Resistors On LVDT Products
  • TSSOP Packaging (33 Only)
  • Complies With TIA/EIA-644 (LVDS)
  • Active Failsafe Assures a High-Level Output With No Input
  • Bus-Pin ESD Protection Exceeds 15 kV HBM
  • Input Remains High-Impedance on Power Down
  • TTL Inputs Are 5-V Tolerant
  • Pin-Compatible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B

1 The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from –40°C to 85°C.

This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet High Speed Differential Receivers datasheet (Rev. B) 04 Nov 2004
Application brief LVDS to Improve EMC in Motor Drives 27 Sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 Aug 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 May 2018
Application note An Overview of LVDS Technology 05 Oct 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

SN65LVDS31-33EVM — Evaluation Module for SN65LVDS31 and SN65LVDS33

TI offers a series of low-voltage differential signaling (LVDS) evaluation modules (EVMs) designed for analysis of the electrical characteristics of LVDS drivers and receivers. Four unique EVMs are available to evaluate the different classes of LVDS devices offered by TI.

As seen in the Combination (...)

User guide: PDF
Not available on TI.com
Simulation model

SN65LVDS33 IBIS Model (Rev. A)

SLLC069A.ZIP (6 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Reference designs

TIDA-060017 — Transmitting SPI Signals Over LVDS Interface Reference Design

This reference design demonstrates how to resolve and optimize signal integrity challenges typically found when sending SPI signals over longer distance on the same PCB or off PCB to another board in a noisy environment by transmitting SPI signals over an LVDS interface. The concept offers (...)
Design guide: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

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