SN75LVDS83 is not recommended for new designs.
This product continues to be in production to support existing customers. Please consider one of these alternatives:
Similar functionality to the compared device.
SN75LVDS83B ACTIVE 10- to 135-MHz 28-bit LVDS transmitter/serializer & FlatLink™ integrated circuit SN75LVDS83B supports a wider PLL frequency range of 10-85MHz and the SN75LVDS83C supports a PLL frequency range of 10-135MHz.

Product details


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  • 4:28 Data Channel Compression at up to 238 MBytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
  • 28 Data Channels and Clock-In Low-Voltage TTL
  • 4 Data Channels and Clock-Out Low-Voltage Differential
  • Operates From a Single 3.3-V Supply With 250 mW (Typ)
  • ESD Protection Exceeds 6 kV
  • 5-V Tolerant Data Inputs
  • Selectable Rising or Falling Edge-Triggered Inputs
  • Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range . . . 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Improved Replacement for the DS90C581

FlatLink is a registered trademark of Texas Instruments.

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The SN75LVDS83 FlatLink transmitter contains four 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and five low-voltage differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit links with the SN75LVDS86 receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL) terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all internal registers to a low level.

The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0°C to 70°C.

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Technical documentation

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Type Title Date
* Data sheet FlatLink (tm) Transmitters datasheet (Rev. I) May 19, 2009
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs Nov. 09, 2018
Application note Flatlink Data Transmission System Design Overview (Rev. A) Jun. 01, 2001
Application note Time Budgeting of the Flatlink Interface Application Report Jun. 11, 1997

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