±10-A 5.7kV RMS single channel isolated gate driver for SiC/IGBT
Product details
Parameters
Package | Pins | Size
Features
- 5.7-kVRMS single channel isolated gate driver
- SiC MOSFETs and IGBTs up to 2121Vpk
- 33-V maximum output drive voltage (VDD-VEE)
- ±10-A drive strength and split output
- 150-V/ns minimum CMTI
- 200-ns response time fast DESAT protection
- 4-A Internal active miller clamp
- 400-mA soft turn-off when fault happens
- Isolated analog sensor with PWM output for
- Temperature sensing with NTC, PTC or thermal diode
- High voltage DC-Link or phase voltage
- Alarm FLT on over current and reset from RST/EN
- Fast enable/disable response on RST/EN
- Reject <40-ns noise transient and pulse on input pins
- 12-V VDD UVLO with power good on RDY
- Inputs/outputs with over/under-shoot transient voltage Immunity up to 5 V
- 130-ns (maximum) propagation delay and 30-ns (maximum) pulse/part skew
- SOIC-16 DW package with creepage and clearance distance > 8mm
- Operating junction temperature –40°C to 150°C
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Description
The UCC21750 is a galvanic isolated single channel gate driver designed for SiC MOSFETs and IGBTs up to 2121-V DC operating voltage with advanced protection features, best-in-class dynamic performance and robustness. UCC21750 has up to ±10-A peak source and sink current.
The input side is isolated from the output side with SiO2 capacitive isolation technology, supporting up to 1.5-kVRMS working voltage, 12.8-kVPK surge immunity with longer than 40 years Isolation barrier life, as well as providing low part-to-part skew, and >150V/ns common mode noise immunity (CMTI).
The UCC21750 includes the state-of-art protection features, such as fast overcurrent and short circuit detection, shunt current sensing support, fault reporting, active miller clamp, and input and output side power supply UVLO to optimize SiC and IGBT switching behavior and robustness. The isolated analog to PWM sensor can be utilized for easier temperature or voltage sensing, further increasing the drivers versatility and simplifying the system design effort, size and cost.
Same functionality but is not pin-for-pin or parametrically equivalent to the compared device:
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- 10-A peak, split output drive current with programmable drive voltages
- Two 5.7-kVrms reinforced isolated channels to support up to 1700 V input rail
- Short circuit protection using desat signal with soft turn OFF and Miller clamp with internal FET
- Robust noise-immune solution with CMTI > 100 V/ns
Software development
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (DW) | 16 | View options |
Ordering & quality
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