Product details


Bus voltage (Max) (V) 120 Power switch MOSFET Input VCC (Min) (V) 8 Input VCC (Max) (V) 16 Peak output current (A) 3.5 Rise time (ns) 12 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 8 Rating Catalog Number of channels (#) 2 Fall time (ns) 10 Prop delay (ns) 16 Iq (uA) 2 Input threshold TTL Channel input logic TTL Negative voltage handling at HS pin (V) -14 Features External Bootstrap Diode open-in-new Find other Half-bridge drivers

Package | Pins | Size

SOIC (D) 8 19 mm² 4.9 x 3.9 open-in-new Find other Half-bridge drivers


  • Drives two N-channel MOSFETs in high-side low-side configuration
  • 16-ns typical propagation delay
  • 12-ns rise, 10-ns typical fall time with 1800-pF load
  • 1-ns typical delay matching
  • Configurable external bootstrap diode
  • 8-V typical undervoltage lockout
  • Absolute maximum negative voltage handling on inputs (–5 V)
  • Absolute maximum negative voltage handling on HS (–14 V)
  • 3.5-A sink, 2.5-A Source output currents
  • Absolute maximum boot voltage 120 V
  • Inputs are independent of each other and VDD
  • Under voltage lockout for both channels
  • Specified from –40°C to 140°C junction temperature

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open-in-new Find other Half-bridge drivers


The UCC27288 is a robust N-channel MOSFET driver with a maximum switch node (HS) voltage rating of 100 V. It allows for two N-channel MOSFETs to be controlled in half-bridge or synchronous buck configuration based topologies. Its 3.5-A peak sink current and 2.5-A peak source current along with low pull-up and pull-down resistance allows the UCC27288 to drive large power MOSFETs with minimum switching losses during the transition of the MOSFET Miller plateau. Since the inputs are independent of the supply voltage, UCC27288 can be used in conjunction with both analog and digital controllers. Two inputs are completely independent of each other and therefore provides added control design flexibility.

The input pins as well as the HS pin are able to tolerate significant negative voltage, which improves system robustness. The inputs are completely independent of each other. This allows for control flexibility where two outputs can be overlapped by overlapping inputs if needed. Small propagation delay and delay matching specifications minimize the dead-time requirement which improves system efficiency.

Under voltage lockout (UVLO) is provided for both the high-side and low-side driver stages forcing the outputs low if the VDD voltage is below the specified threshold. No integrated bootstrap diode allows user to use application-appropriate external bootstrap diode. UCC27288 is offered in an SOIC8 package to improve system robustness in harsh environments.

open-in-new Find other Half-bridge drivers
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Technical documentation

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Type Title Date
* Data sheet UCC27288 2.5-A/3.5-A 120-V Half-Bridge Driver with 8-V UVLO and External Bootstrap Diode datasheet (Rev. A) Aug. 14, 2020
Application note Understanding and comparing peak current capability of gate drivers Mar. 30, 2021
User guide Using the UCC27288EVM Jun. 16, 2020
Certificate UCC27288EVM EU Declaration of Conformity (DoC) May 13, 2020
Application note Implementing High-Side Switches Using Half-Bridge Gate Drivers for 48-V Battery. May 12, 2020
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse Sep. 19, 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime May 30, 2018
Technical article Boosting efficiency for your solar inverter designs May 24, 2018
Technical article How to achieve higher system robustness in DC drives, part 1: negative voltage Apr. 17, 2018

Design & development

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Hardware development

document-generic User guide
UCC27288EVM is designed for evaluating UCC27288D, which is a 100-V half bridge gate driver with 2.5-A peak source current and 3.5-A peak sink current capability. This EVM serves as a reference design for driving power MOSFETs with up to 20-V drive voltage.
  • Up to 20-V power supply range
  • 2.5-A and 3.5-A source/sink current capability
  • PCB layout optimized for power supply bypassing capacitance and gate drive loop

Design tools & simulation

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SOIC (D) 8 View options

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