The UCC27288 is a robust N-channel MOSFET driver with a maximum switch node (HS) voltage rating of 100 V. It allows for two N-channel MOSFETs to be controlled in half-bridge or synchronous buck configuration based topologies. Its 3-A peak source and sink current along with low pull-up and pull-down resistance allows the UCC27288 to drive large power MOSFETs with minimum switching losses during the transition of the MOSFET Miller plateau. Since the inputs are independent of the supply voltage, UCC27288 can be used in conjunction with both analog and digital controllers. Two inputs are completely independent of each other and therefore provides added control design flexibility.
The input pins as well as the HS pin are able to tolerate significant negative voltage, which improves system robustness. The inputs are completely independent of each other. This allows for control flexibility where two outputs can be overlapped by overlapping inputs if needed. Small propagation delay and delay matching specifications minimize the dead-time requirement which improves system efficiency.
Under voltage lockout (UVLO) is provided for both the high-side and low-side driver stages forcing the outputs low if the VDD voltage is below the specified threshold. No integrated bootstrap diode allows user to use application-appropriate external bootstrap diode. UCC27288 is offered in an SOIC8 package to improve system robustness in harsh environments.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | UCC27288 3-A 120-V Half-Bridge Driver with 8-V UVLO and External Bootstrap Diode datasheet (Rev. B) | PDF | HTML | 22 Apr 2022 |
| Application note | Understanding and comparing peak current capability of gate drivers | PDF | HTML | 30 Mar 2021 | |
| EVM User's guide | Using the UCC27288EVM | 16 Jun 2020 | ||
| Certificate | UCC27288EVM EU Declaration of Conformity (DoC) | 13 May 2020 | ||
| Application note | Implementing High-Side Switches Using Half-Bridge Gate Drivers for 48-V Battery. | 12 May 2020 | ||
| Technical article | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | 19 Sep 2018 | ||
| Technical article | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | 30 May 2018 | ||
| Technical article | Boosting efficiency for your solar inverter designs | 24 May 2018 | ||
| Technical article | How to achieve higher system robustness in DC drives, part 1: negative voltage | 17 Apr 2018 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | Download |
|---|---|---|
| SOIC (D) | 8 | View options |
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