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AM6411

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Single-Core 64-Bit-Arm® Cortex®-A53, Single-Core Cortex-R5F, PCIe, USB 3.0 und Sicherheit

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AM6411

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Produktdetails

CPU 1 Arm Cortex-A53 Frequency (MHz) 800, 1000 Coprocessors 1 Arm Cortex-R5F Protocols Ethernet, TSN PCIe 1 PCIe Gen 2 Hardware accelerators CPU only, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Hardware-enforced isolation, Secure boot, Secure debug Rating Catalog Power supply solution TPS65219, TPS65220 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
CPU 1 Arm Cortex-A53 Frequency (MHz) 800, 1000 Coprocessors 1 Arm Cortex-R5F Protocols Ethernet, TSN PCIe 1 PCIe Gen 2 Hardware accelerators CPU only, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Hardware-enforced isolation, Secure boot, Secure debug Rating Catalog Power supply solution TPS65219, TPS65220 Operating temperature range (°C) -40 to 125 Edge AI enabled Yes
FCBGA (ALV) 441 295.84 mm² 17.2 x 17.2

Processor cores:

  • 1× Dual 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.0GHz
    • Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems at up to 800MHz, integrated for real-time processing
    • Dual-core Arm Cortex-R5F supports dual-core and single-core modes
    • 32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC

Industrial subsystem:

  • 2× gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and more
    • Backward compatibility with 10/100Mb PRU_ICSS
    • Each PRU_ICSSG contains:
      • 2× Ethernet ports
        • MII (10/100)
        • RGMII (10/100/1000)
      • 6 PRU RISC cores per PRU_ICSSG each core having:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • Two 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta filters
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • One Enhanced Capture Module (ECAP)
      • 16550-compatible UART with a dedicated 192MHz clock to support 12Mbps PROFIBUS

Memory subsystem:

  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600MT/s
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-Bit parallel bus with 133MHz clock or
    • 32-Bit parallel bus with 100MHz clock
    • Error Location Module (ELM) support

System on Chip (SoC) Services:

  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals

  • Data Movement Subsystem (DMSS)

    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-speed interfaces:

  • 1× Integrated Ethernet switch (CPSW3G) supporting:
    • Up to 2 Ethernet ports
      • RMII (10/100)
      • RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 operation
    • Supports Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB host,USB device, orUSB Dual-Role device
    • USB device: High-speed (480Mbps), andFull-speed (12Mbps)
    • USB host: SuperSpeed Gen 1 (5Gbps),High-speed (480Mbps),Full-speed (12Mbps), andLow-speed (1.5Mbps)

General connectivity:

  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× configurable Universal Asynchronous Receive/Transmit (UART) modules
  • 1× Flash Subsystem (FSS) that can be configured as Octal SPI (OSPI) flash interfaces or one Quad SPI (QSPI)
  • 1× 12-Bit Analog-to-Digital Converters (ADC)
    • Up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
  • 6× Fast Serial Interface Receiver (FSI_RX) cores
  • 2× Fast Serial Interface Transmitter (FSI_TX) cores
  • 3× General-Purpose I/O (GPIO) modules

Control interfaces:

  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD support

Media and data storage:

  • 2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
    • One 4-bit for SD/SDIO;
    • One 8-bit for eMMC
    • Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cards

Power management:

  • Simplified power sequence
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for safety monitoring of over-under voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional Safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
  • Functional Safety Features
    • ECC or parity on calculation-critical memories
    • ECC and parity on select internal bus interconnect
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with error pin
    • Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
    • Dedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Dedicated PLL
      • Dedicated I/O supply
      • Separate reset

SoC architecture:

  • Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB, PCIe, and Ethernet interfaces
  • 16nm FinFET technology
  • 17.2mm × 17.2mm, 0.8mm pitch, 441-pin BGA package

Processor cores:

  • 1× Dual 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.0GHz
    • Dual-core Cortex-A53 cluster with 256KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Up to 2× Dual-core Arm Cortex-R5F MCU subsystems at up to 800MHz, integrated for real-time processing
    • Dual-core Arm Cortex-R5F supports dual-core and single-core modes
    • 32KB ICache, 32KB DCache and 64KB TCM per each R5F core for a total of 256KB TCM with SECDED ECC on all memories
  • 1× Single-core Arm Cortex-M4F MCU at up to 400MHz
    • 256KB SRAM with SECDED ECC

Industrial subsystem:

  • 2× gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Supports Profinet IRT, Profinet RT, EtherNet/IP, EtherCAT, Time-Sensitive Networking (TSN), and more
    • Backward compatibility with 10/100Mb PRU_ICSS
    • Each PRU_ICSSG contains:
      • 2× Ethernet ports
        • MII (10/100)
        • RGMII (10/100/1000)
      • 6 PRU RISC cores per PRU_ICSSG each core having:
        • Instruction RAM with ECC
        • Broadside RAM
        • Multiplier with optional accumulator (MAC)
        • CRC16/32 hardware accelerator
        • Byte swap for Big/Little Endian conversion
        • SUM32 hardware accelerator for UDP checksum
        • Task Manager for preemption support
      • Three Data RAMs with ECC
      • 8 banks of 30 × 32-bit register scratchpad memory
      • Interrupt controller and task manager
      • Two 64-bit Industrial Ethernet Peripherals (IEPs) for time stamping and other time synchronization functions
      • 18× Sigma-Delta filters
        • Short circuit logic
        • Over-current logic
      • 6× Multi-protocol position encoder interfaces
      • One Enhanced Capture Module (ECAP)
      • 16550-compatible UART with a dedicated 192MHz clock to support 12Mbps PROFIBUS

Memory subsystem:

  • Up to 2MB of On-chip RAM (OCSRAM) with SECDED ECC:
    • Can be divided into smaller banks in increments of 256KB for as many as 8 separate memory banks
    • Each memory bank can be allocated to a single core to facilitate software task partitioning
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600MT/s
  • 1× General-Purpose Memory Controller (GPMC)
    • 16-Bit parallel bus with 133MHz clock or
    • 32-Bit parallel bus with 100MHz clock
    • Error Location Module (ELM) support

System on Chip (SoC) Services:

  • Device Management Security Controller (DMSC-L)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, and clock/reset/power management
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals

  • Data Movement Subsystem (DMSS)

    • Block Copy DMA (BCDMA)
    • Packet DMA (PKTDMA)
    • Secure Proxy (SEC_PROXY)
    • Ring Accelerator (RINGACC)

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Secure watchdog/timer/IPC
    • Extensive firewall support for isolation
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Security co-processor (DMSC-L) for key and security management, with dedicated device level interconnect for security
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-speed interfaces:

  • 1× Integrated Ethernet switch (CPSW3G) supporting:
    • Up to 2 Ethernet ports
      • RMII (10/100)
      • RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • Energy efficient Ethernet (802.3az)
  • 1× PCI-Express Gen2 controller (PCIE)
    • Supports Gen2 operation
    • Supports Single Lane operation
  • 1× USB 3.1 Dual-Role Device (DRD) Subsystem (USBSS)
    • Port configurable as USB host,USB device, orUSB Dual-Role device
    • USB device: High-speed (480Mbps), andFull-speed (12Mbps)
    • USB host: SuperSpeed Gen 1 (5Gbps),High-speed (480Mbps),Full-speed (12Mbps), andLow-speed (1.5Mbps)

General connectivity:

  • 6× Inter-Integrated Circuit (I2C) ports
  • 9× configurable Universal Asynchronous Receive/Transmit (UART) modules
  • 1× Flash Subsystem (FSS) that can be configured as Octal SPI (OSPI) flash interfaces or one Quad SPI (QSPI)
  • 1× 12-Bit Analog-to-Digital Converters (ADC)
    • Up to 4MSPS
    • 8× multiplexed analog inputs
  • 7× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
  • 6× Fast Serial Interface Receiver (FSI_RX) cores
  • 2× Fast Serial Interface Transmitter (FSI_TX) cores
  • 3× General-Purpose I/O (GPIO) modules

Control interfaces:

  • 9× Enhanced Pulse-Width Modulator (EPWM) modules
  • 3× Enhanced Capture (ECAP) modules
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2× Modular Controller Area Network (MCAN) modules with or without full CAN-FD support

Media and data storage:

  • 2× Multi-Media Card/Secure Digital (MMC/SD/SDIO) interfaces
    • One 4-bit for SD/SDIO;
    • One 8-bit for eMMC
    • Integrated analog switch for voltage switching between 3.3V to 1.8V for high-speed cards

Power management:

  • Simplified power sequence
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated voltage supervisor for safety monitoring of over-under voltage conditions
  • Integrated power supply glitch detector for detecting fast supply transients

Functional Safety:

  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware integrity up to SIL 2
    • Safety-related certification
  • Functional Safety Features
    • ECC or parity on calculation-critical memories
    • ECC and parity on select internal bus interconnect
    • Built-In Self-Test (BIST) for CPU and on-chip RAM
    • Error Signaling Module (ESM) with error pin
    • Runtime safety diagnostics, voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engine for memory integrity checks
    • Dedicated MCU domain memory, interfaces, and M4F core capable of being isolated from the larger SoC with Freedom From Interference (FFI) features
      • Separate interconnect
      • Firewalls and timeout gaskets
      • Dedicated PLL
      • Dedicated I/O supply
      • Separate reset

SoC architecture:

  • Supports primary boot from UART, I2C, OSPI/QSPI Flash, SPI Flash, parallel NOR Flash, parallel NAND Flash, SD, eMMC, USB, PCIe, and Ethernet interfaces
  • 16nm FinFET technology
  • 17.2mm × 17.2mm, 0.8mm pitch, 441-pin BGA package

AM64x is an extension of the Sitara™ Industrial-grade family of heterogeneous Arm® processors. AM64x is built for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a unique combination of real-time processing and communications with applications processing. AM64x combines two instances of the Sitara device’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU.

AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these systems.

The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux world with the real-time world by enabling isolation between Linux applications and real-time streams through configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.

The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT SubDevice, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.

AM64x is an extension of the Sitara™ Industrial-grade family of heterogeneous Arm® processors. AM64x is built for industrial applications, such as motor drives and Programmable Logic Controllers (PLCs), which require a unique combination of real-time processing and communications with applications processing. AM64x combines two instances of the Sitara device’s gigabit TSN-enabled PRU-ICSSG with up to two Arm® Cortex®-A53 cores, up to four Cortex-R5F MCUs, and a Cortex-M4F MCU.

AM64x is architected to provide real-time performance through the high-performance R5Fs, Tightly-Coupled Memory banks, configurable SRAM partitioning, and dedicated low-latency paths to and from peripherals for rapid data movement in and out of the SoC. This deterministic architecture allows for AM64x to handle the tight control loops found in servo drives while the peripherals like FSI, GPMC, PWMs, sigma delta decimation filters, and absolute encoder interfaces help enable a number of different architectures found in these systems.

The Cortex-A53s provide the powerful computing elements necessary for Linux applications. Linux, and Real-time (RT) Linux, is provided through TI’s Processor SDK Linux which stays updated to the latest Long Term Support (LTS) Linux kernel, bootloader and Yocto file system on an annual basis. AM64x helps bridge the Linux world with the real-time world by enabling isolation between Linux applications and real-time streams through configurable memory partitioning. The Cortex-A53s can be assigned to work strictly out of DDR for Linux, and the internal SRAM can be broken up into various sizes for the Cortex-R5Fs to use together or independently.

The AM64x provides flexible industrial communications capability including full protocol stacks for EtherCAT SubDevice, PROFINET device, EtherNet/IP adapter, and IO-Link Master. The PRU-ICSSG further provides capability for gigabit and TSN based protocols. In addition, the PRU-ICSSG also enables additional interfaces in the SoC including sigma delta decimation filters and absolute encoder interfaces.

Functional safety features can be enabled through the integrated Cortex-M4F along with dedicated peripherals which can all be isolated from the rest of the SoC. AM64x also supports secure boot.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet AM64x Sitara™ Processors datasheet (Rev. H) PDF | HTML 19 Dez 2025
* Errata AM64x/AM243x Processor Silicon Revision 1.0, 2.0 (Rev. J) PDF | HTML 13 Nov 2025
Application note Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 24 Nov 2025
User guide Hardware Design Considerations for Custom Board Using AM6442, AM6422, AM6412 and AM2434 (ALV, ALX) Processor (Rev. D) PDF | HTML 24 Okt 2025
Application note Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. H) PDF | HTML 17 Okt 2025
User guide AM6442 , AM6422 , AM6412 and AM2434 Processor Schematic Design Guidelines and Schematic Review Checklist (Rev. E) PDF | HTML 10 Okt 2025
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 05 Sep 2025
Application note Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 03 Sep 2025
Functional safety information AM6x, AM24x Software Diagnostics Library TÜV SÜD Functional Safety Certificate for 9.2.0 SDK (Rev. A) 17 Jul 2025
White paper Securing Arm-Based Application Processors (Rev. F) PDF | HTML 26 Feb 2025
Application note Basic Ethernet Interface Debug With Linux PDF | HTML 11 Okt 2024
Functional safety information AM64x, AM243x IEC61508 TUV SUD Functional Safety Certificate 25 Mär 2024
Application note Sitara™AM64x /AM243x BenchmarksCortex-R5 Memory Access Latency (Rev. B) PDF | HTML 24 Jan 2024
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15 Nov 2023
User guide AM64x/AM243x Technical Reference Manual (Rev. H) 01 Nov 2023
Application note Integration of MbedTLS on SITARA MCU Devices PDF | HTML 03 Aug 2023
Application note Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 24 Mai 2023
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24 Feb 2023
Application note PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 11 Okt 2022
Application note Powering the AM64x with the TPS65220 or TPS65219 PMIC PDF | HTML 22 Sep 2022
Application note Optimized Trigonometric Functions on TI Arm Cores (Rev. A) PDF | HTML 08 Aug 2022
Application note AM64x/AM243x Extended Power-On Hours PDF | HTML 05 Aug 2022
Application note AM243x/AM64x Single Chip Motor Control Benchmark PDF | HTML 30 Mär 2022
Application note Using LP8733xx and TPS65218xx PMICs to Power AM64x and AM243x Sitara Processors PDF | HTML 16 Feb 2022
More literature Quick Start Guide for Wi-SUN® Wireless MCUs and Transceivers PDF | HTML 14 Jan 2022
Application brief Powering the AM64xx With the LP8733xx PMIC PDF | HTML 15 Jul 2021
Application note AM64x/AM243x DDR Board Design and Layout Guidelines (Rev. A) PDF | HTML 01 Jul 2021
Application note AM64x/AM243x Power Estimation Tool (Rev. A) PDF | HTML 01 Jul 2021
Technical article We designed a Linux gateway for you. Here’s how you can use it in your next buildi PDF | HTML 18 Mai 2021
User guide AM64x/AM243x BGA Escape Routing (Rev. A) PDF | HTML 06 Apr 2021
More literature Decentralized servo architecture webinar 01 Mär 2021
Technical article Compact. Precise. Connected. Increase productivity with intelligent edge computing PDF | HTML 01 Feb 2021
More literature From Start to Finish: A Product Development Roadmap for Sitara™ Processors 16 Dez 2020

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Verfügbare Lösungen für die Stromversorgung für den AM6411 finden. TI bietet Stromversorgungslösungen für Ein-Chip-Systeme (SoCs), Prozessoren, Mikrocontroller, Sensoren und feldprogrammierbare Gate-Arrays (FPGAs) von TI und von Fremdherstellern an.

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Debug-Tastkopf

TMDSEMU110-U — XDS110 JTAG-Debug-Tastkopf

Der XDS110 von Texas Instruments ist eine neue Klasse von Debug-Tastkopf (Emulator) für Embedded-Prozessoren von TI. Der XDS110 ersetzt die XDS100-Familie und unterstützt eine größere Anzahl von Standards (IEEE1149.1, IEEE1149.7, SWD) in einem einzigen Pod. Alle XDS-Debug-Tastköpfe unterstützen (...)

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Debug-Tastkopf

TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

Der XDS200 ist ein Debug-Tastkopf (Emulator) zum Debugging von Embedded-Bausteinen von TI. Für die meisten Bausteine wird die Verwendung der neueren, kostengünstigeren XDS110 (www.ti.com/tool/TMDSEMU110-U) empfohlen. Der XDS200 unterstützt eine große Zahl von Standards (IEEE1149.1, IEEE1149.7, SWD) (...)

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Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7).  Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

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Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Debug-Tastkopf

LB-3P-TRACE32-ARM — Debug- und Trace-System Lauterbach TRACE32® für Arm®-basierte Mikrocontroller und Prozessoren

Die TRACE32®-Tools von Lauterbach sind eine Suite hochmoderner Hardware- und Softwarekomponenten, mit denen Entwickler alle Arten von Arm®-basierten Mikrocontrollern und Prozessoren analysieren, optimieren und zertifizieren können. Die weltweit anerkannten Debugging- und Trace-Lösungen für (...)

Von: Lauterbach GmbH
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Debug-Tastkopf

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

Von: TASKING Germany GmbH
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Third-party accessory

VANTRON-3P-AM6411 — Vantron Technology G405 Edge-Computing-Gateway mit 2 Ethernet- und 2 Komm.-Anschlüssen

G405 industrial edge computing gateway is an Arm®-based high-performance solution built for industrial applications. The gateway features dual-SIM 4G connectivity, Wi-Fi, Bluetooth, and five Ethernet jacks, while supporting a virtual private network (VPN) to address diversified networking (...)

Von: Vantron Technology, Inc.
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Software-Entwicklungskit (SDK)

IBV-3P-ICECAT — IBV EtherCAT MainDevice SDK für eingebettete Systeme

The icECAT EtherCAT Master Stack library by IBV is a Software Development Kit (SDK) for creating an EtherCAT MainDevice (master) system achieving best performance with lowest resource usage. It is especially designed for use on embedded systems with optimized Link Layer drivers with DMA support (...)
Von: IBV - Echtzeit- und Embedded GmbH & Co. KG
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Software-Entwicklungskit (SDK)

MCU-PLUS-SDK-AM64X — MCU+ SDK RTOS/NO-RTOS for AM64x

The Processor and MCU+ SDKs (Software Development Kits) are unified software platforms for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of these SDKs are consistent across TI’s broad portfolio for which they are provided, (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-AM64X — Processor SDK Linux for AM64x

The Processor and MCU+ SDKs (Software Development Kits) are unified software platforms for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of these SDKs are consistent across TI’s broad portfolio for which they are provided, (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-RT-AM64X — Processor SDK RT-Linux for AM64x

The Processor and MCU+ SDKs (Software Development Kits) are unified software platforms for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of these SDKs are consistent across TI’s broad portfolio for which they are provided, (...)

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Firmware

DDR-MARGIN-FW — Firmware and scripts to measure system DDR margin

The DDR margin firmware and supporting scripts allow visualization and measurement of system margin in the DDR interface on board. These tools enable probe-less measurement of critical data signals to understand the integrity and robustness of the interface.
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Firmware

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM Firmware

Das SecIC-HSM wurde entwickelt, um die für MCU-/SoC-Chips erforderlichen Cybersicherheitsanforderungen zu erfüllen. Die HSM-Firmware kann in Bereichen wie Automobil, alternative Energieerzeugung, Photovoltaik, Robotik, Gesundheitswesen und Luftfahrt eingesetzt werden. Zu den bereitgestellten (...)
Von: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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Firmware

USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC-Algorithmus-Firmware

Die Sicherheitslösungen von Uni-Sentry verwenden PQC-Algorithmen, die Entschlüsselungsbedrohungen durch Quantencomputer gegenüber herkömmlichen kryptografischen Algorithmen abwehren können. Die PQC-Firmware ist gemeinsam mit dem Hardware-Sicherheitsmodul (HSM) optimiert, sodass (...)
Von: Shanghai Uni-Sentry Intelligent Technology Co., LTD
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Erste Schritte

TI-DEVELOPER-ZONE — Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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IDE, Konfiguration, Compiler oder Debugger

CLOCKTREE-AM64X — Clock tree configuration for AM64x


The Clock Tree Tool (CTT) for ARM Processors & Digital Signal Processors is an interactive configuration software tool that provides information about device clock tree architecture. This tool allows visualization of the device clock tree. It can also be used to determine the exact register (...)

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IDE, Konfiguration, Compiler oder Debugger

DDR-CONFIG-AM64 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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IDE, Konfiguration, Compiler oder Debugger

K3-RESOURCE-CONFIGURATION — Resource partitioning tool for multi core SOCs

Also known as the k3-respart-tool, the Resource Configuration tool allows for configuration of various system level parameters and generate the necessary data to be fed into software components
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IDE, Konfiguration, Compiler oder Debugger

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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Onlineschulungen

AM64-ACADEMY — AM64x Academy

Designed to simplify and accelerate custom AM64x development.
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Betriebssystem (BS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Von: Green Hills Software
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Betriebssystem (BS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
Von: Green Hills Software
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Betriebssystem (BS)

TRZN-3P-TORIZON-OS — Einsatzbereite Industrial Embedded-Linux-Verteilung Torizon OS

Torizon OS ist ein kostenloses, quelloffenes Industrial Embedded-Linux-Betriebssystem, das auf die Vereinfachung der Entwicklung und Wartung von Produkten ausgelegt ist, die hohe Zuverlässigkeit und Sicherheit erfordern. Neben anderen zentralen Funktionen bietet es eine optimale Containerlaufzeit (...)
Von: Torizon
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Betriebssystem (BS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS Vorzertifiziertes Sicherheits-RTOS

SAFERTOS® ist ein einzigartiges Echtzeitbetriebssystem für Embedded-Prozessoren. Er ist vom TÜV SÜD nach den Normen IEC 61508 SIL3 und ISO 26262 ASILD vorzertifiziert. SAFERTOS® wurde vom Expertenteam von WHIS speziell auf Sicherheit ausgelegt und wird weltweit in sicherheitskritischen Anwendungen (...)
Von: WITTENSTEIN High Integrity Systems
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Support-Software

VLAB-3P-V-EVM — Virtuelle ASTC VLAB-Entwicklungsplattformen und -Tools

VLAB Works ist der Branchenführer in der Softwaretechnologie für die Modellierung, Simulation und virtuelle Prototypenentwicklung von eingebetteten elektronischen Systemen. VLAB Technologien und Lösungen ermöglichen die Anwendung von Automatisierung und agilen Prozessen bei der Entwicklung von (...)
Von: VLAB Works
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Simulationsmodell

AM64x IBIS-AMI Model

SPRM731.ZIP (44474 KB) - IBIS-AMI Model
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Simulationsmodell

AM64x SR2.0 IBIS Model

SPRM810.ZIP (1889 KB) - IBIS Model
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Simulationsmodell

AM64x/AM243x BSDL Model

SPRM732.ZIP (21 KB) - BSDL Model
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Simulationsmodell

AM64x/AM243x IBIS Model (Rev. E)

SPRM730E.ZIP (1889 KB) - IBIS Model
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Simulationsmodell

AM64x/AM243x Thermal Model (Rev. A)

SPRM773A.ZIP (1 KB) - Thermal Model
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Berechnungstool

SPRM779 — AM64x Power Estimation Tool

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Berechnungstool

SPRR451 — AM64x Maximum Current Ratings

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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
FCBGA (ALV) 441 Ultra Librarian
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