DS90LV001

AKTIV

LVDS-Puffer, 800 Mbit/s

Produktdetails

Function Buffer Protocols LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 800 Input signal LVCMOS, LVDS, LVPECL, LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer Protocols LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 800 Input signal LVCMOS, LVDS, LVPECL, LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) WSON (NGK) 8 9 mm² (3 mm × 3 mm)
  • Single +3.3 V Supply
  • LVDS Receiver Inputs Accept LVPECL Signals
  • TRI-STATE Outputs
  • Receiver Input Threshold < ±100 mV
  • Fast Propagation Delay of 1.4 ns (Typ)
  • Low Jitter 800 Mbps Fully Differential Data Path
  • 100 ps (Typ) of pk-pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps
  • Compatible with ANSI/TIA/EIA-644-A LVDS Standard
  • 8 pin SOIC and Space Saving (70%) WSON Package
  • Industrial Temperature Range

All trademarks are the property of their respective owners.

  • Single +3.3 V Supply
  • LVDS Receiver Inputs Accept LVPECL Signals
  • TRI-STATE Outputs
  • Receiver Input Threshold < ±100 mV
  • Fast Propagation Delay of 1.4 ns (Typ)
  • Low Jitter 800 Mbps Fully Differential Data Path
  • 100 ps (Typ) of pk-pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps
  • Compatible with ANSI/TIA/EIA-644-A LVDS Standard
  • 8 pin SOIC and Space Saving (70%) WSON Package
  • Industrial Temperature Range

All trademarks are the property of their respective owners.

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS90LV001, available in the WSON package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator.

An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin WSON and SOIC.

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS90LV001, available in the WSON package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator.

An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin WSON and SOIC.

Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 5
Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt DS90LV001 800 Mbps LVDS Buffer datasheet (Rev. E) 22.04.2013
Application brief How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver 09.01.2019
Anwendungshinweis Signaling Rate vs. Distance for Differential Buffers 26.01.2010
Whitepaper Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches 01.08.2001
Anwendungshinweis An Overview of LVDS Technology 05.10.1998

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Simulationsmodell

DS90LV001 IBIS Model

SNLM045.ZIP (29 KB) - IBIS-Modell
Unterstützte Produkte und Hardware
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
SOIC (D) 8 Ultra Librarian
WSON (NGK) 8 Ultra Librarian

Bestellen & Qualität

Empfohlene Produkte können Parameter, Evaluierungsmodule oder Referenzdesigns zu diesem TI-Produkt beinhalten.

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos