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The LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer retimes serial digital video data conforming to the SMPTE 259M (C) standard. The LMH0036 operates at the serial data rate of 270 Mbps, and also supports DVB-ASI operation at 270 Mbps. The LMH0036 includes an integrated 4:1 input multiplexer for selecting one of four input data streams for retiming.
The LMH0036 retimes the incoming data to suppress accumulated jitter. The LMH0036 recovers the serial data-rate clock and optionally provides it as an output. The LMH0036 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD indicator output, lock detect output, auto/manual data bypass, and output mute. The serial data inputs, outputs, and serial data-rate clock outputs are differential LVPECL compatible. The CML serial data and serial data-rate clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible.
The LMH0036 is powered from a single 3.3V supply. Power dissipation is typically 360 mW. The device is housed in a 48-pin WQFN package.
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | LMH0036 SD SDI Reclocker with 4:1 Input Multiplexer datasheet (Rev. B) | 15 Apr 2013 | |
| Selection guide | Broadcast and Professional Video Interface Solutions (Rev. E) | 05 Apr 2017 | ||
| Application note | AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) | 26 Apr 2013 | ||
| Application note | AN-2145 Power Considerations for SDI Products (Rev. B) | 26 Apr 2013 | ||
| Application note | AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) | 26 Apr 2013 | ||
| Application note | Replacing the CLC012 Adaptive Cable Equalizer with the LMH0074 (Rev. A) | 26 Apr 2013 | ||
| Application note | Replacing the CLC014 Adaptive Cable Equalizer with the LMH0074 (Rev. A) | 26 Apr 2013 | ||
| Application note | High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems | 12 Nov 2009 | ||
| Application note | Reference Clock Loop Through Application | 16 Jan 2009 | ||
| Design guide | Broadcast Video Owner's Manual | 17 Nov 2006 |
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| Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
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