CDCEL949
Sintetizador de reloj VCXO programable de 4 PLL con salidas LVCMOS de 1,8 V.
CDCEL949
- Member of programmable clock generator family
- CDCEx913: 1 PLLs, 3 outputs
- CDCEx925: 2 PLLs, 5 outputs
- CDCEx937: 3 PLLs, 7 outputs
- CDCEx949: 4 PLLs, 9 outputs
- In-System programmability and EEPROM
- Serial programmable volatile register
- Nonvolatile EEPROM to store customer settings
- Flexible input clocking concept
- External crystal: 8MHz to 32MHz
- On-chip VCXO pull-range: ±150ppm
- Single-ended LVCMOS up to 160MHz
- Free selectable output frequency up to 230MHz
- Low-noise PLL core
- PLL loop filter components integrated
- Low period jitter: 60ps (typical)
- Separate output supply pins
- CDCE949: 3.3V and 2.5V
- CDCEL949: 1.8V
- Flexible clock driver
- Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
- Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
- Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
- Programmable SSC modulation
- Enables 0ppm clock generation
- 1.8V device core supply
- Wide temperature range: –40°C to 85°C
- Packaged in TSSOP
- Development and programming kit for easy PLL design and programming (TI Pro-Clock™)
The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. These devices generate up to nine output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.
The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.
The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.
All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.
The CDCEx949 operates in a 1.8V environment within a temperature range of –40°C to 85°C.
Documentación técnica
Tipo | Título | Fecha | ||
---|---|---|---|---|
* | Data sheet | CDCE(L)949: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet (Rev. G) | PDF | HTML | 16 ene 2024 |
Application note | VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) | 23 abr 2012 | ||
User guide | CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) | 22 nov 2010 | ||
User guide | CDCE(L)9xx Performance Evaluation Module (Rev. A) | 07 jul 2010 | ||
Application note | Troubleshooting I2C Bus Protocol | 19 oct 2009 | ||
Application note | Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 | 23 sep 2009 | ||
User guide | CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual | 09 dic 2008 | ||
Application note | Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency | 31 mar 2008 | ||
Application note | Practical consideration on choosing a crystal for CDCE(L)9xx family | 24 mar 2008 |
Diseño y desarrollo
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
CDCEL949PERF-EVM — Módulo de evaluación del rendimiento de CDCEL949
The CDCEL949PERF-EVM will help to verify the functionality and performance of CDCEL949 with the options of crystal and 1.8 V LVCMOS inputs. The outputs can be connected to the Oscilloscope directly with SMA cables. The below information/items are included: The EVM use's guide : SCAU022; the (...)
CDCEL9XXPROGEVM — Placa de programación EEPROM de la familia CDCE(L)949
The clock generator CDCE(L)949 family has integrated EEPROM that allows the default frequency settings to be saved upon start up. CDCEL9XXPROGEVM is a programming board that allows a fast programming of prototyping samples or small production quantities. It applies to all 8 devices in the family: (...)
CLOCKPRO — ClockPro Software
TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:
- CDCE949
- CDCE937
- CDCE925
- CDCE913
- CDCE906
- CDCE706
- CDCEL949
- CDCEL937
- CDCEL925
- CDCEL913
It is intended to be used with the evaluation modules of the above devices.
Productos y hardware compatibles
Productos
Generadores de señal de reloj
Desarrollo de hardware
Placa de evaluación
Software
Herramienta de programación de software
SCAC073 — TI-Pro-Clock Programming Software
Productos y hardware compatibles
Productos
Generadores de señal de reloj
CLOCK-TREE-ARCHITECT — Software de programación de diseño de árbol de reloj
PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI
Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
---|---|---|
TSSOP (PW) | 24 | Ultra Librarian |
Pedidos y calidad
- RoHS
- REACH
- Marcado del dispositivo
- Acabado de plomo/material de la bola
- Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
- Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
- Contenido del material
- Resumen de calificaciones
- Monitoreo continuo de confiabilidad
- Lugar de fabricación
- Lugar de ensamblaje
Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.
Soporte y capacitación
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