The SN74HCS596-Q1 device contains an 8-bit, serial-in,
parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include
Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals.
The storage register has parallel open-drain outputs. Separate clocks are provided for both the
shift and storage register. The shift register has a direct overriding clear
(SRCLR) input, serial (SER) input, and a serial output
(QH) for cascading. When the output-enable (OE)
input is high, the outputs are in a high-impedance state. Internal register data is not impacted by
the operation of the OE input.
The SN74HCS596-Q1 device contains an 8-bit, serial-in,
parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include
Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals.
The storage register has parallel open-drain outputs. Separate clocks are provided for both the
shift and storage register. The shift register has a direct overriding clear
(SRCLR) input, serial (SER) input, and a serial output
(QH) for cascading. When the output-enable (OE)
input is high, the outputs are in a high-impedance state. Internal register data is not impacted by
the operation of the OE input.