DS90CF384
- 20 to 65 MHz shift clock support
- Programmable transmitter (DS90C383) strobe select (Rising or Falling edge strobe)
- Single 3.3V supply
- Chipset (Tx + Rx) power consumption < 250 mW (typ)
- Power-down mode (< 0.5 mW total)
- Single pixel per clock XGA (1024×768) ready
- Supports VGA, SVGA, XGA and higher addressability.
- Up to 227 Megabytes/sec bandwidth
- Up to 1.8 Gbps throughput
- Narrow bus reduces cable size and cost
- 290 mV swing LVDS devices for low EMI
- PLL requires no external components
- Low profile 56-lead TSSOP package.
- Also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package
- Falling edge data strobe Receiver
- Compatible with TIA/EIA-644 LVDS standard
- ESD rating >7 kV
- Operating Temperature: -40°C to +85°C
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
The DS90C383 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. Both devices are also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | DS90C383/F384 3.3VProg LVDS Trans 24Bit FPD, 65MHz,3.3VLVDS Rcvr 24Bit FPD(jp) データシート (Rev. A 翻訳版) | 英語版 (Rev.A) | 2004/05/13 | ||
| アプリケーション・ノート | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018/06/29 | ||||
| アプリケーション・ノート | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017/08/08 | ||||
| アプリケーション・ノート | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016/01/13 | |||
| アプリケーション・ノート | Application Note 1032 An Introduction to FPD-Link (jp) | 2009/04/03 | ||||
| アプリケーション・ノート | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004/05/15 | ||||
| アプリケーション・ノート | Application Note 1056 STN Application Using FPD-Link (jp) | 英語版 | 2004/05/14 | |||
| アプリケーション・ノート | 1085 FPD-Link PCB and Interconnect Design-In Guidelines (jp) | 英語版 | 2004/05/14 |
設計と開発
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FLINK3V8BT-85 — FPD-Link ファミリ シリアライザ/ デシリアライザ LVDS 評価キット
FPD-Link evaluation kit contains a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This kit will demonstrate the chipsets interfacing from test equipment or a graphics controller using Low Voltage Differential Signaling (LVDS) to a receiver board.
The Transmitter board (...)
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
購入と品質
推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス デザインが存在する可能性があります。