SN74AUP2G00-Q1
- Qualified for Automotive Applications
- Low Static-Power Consumption
(ICC = 1.7 µA Maximum) - Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typ at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot
<10% of VCC - Ioff Supports Partial-Power-Down Mode Operation
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 5.9 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
The AUP family is TIs premier solution to the industrys low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
The SN74AUP2G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | SN74AUP2G00-Q1 Low-Power Dual 2-Input Positive-NAND Gate データシート | 2010/06/30 | |||
| アプリケーション概要 | シュミット トリガについて (Rev. B 翻訳版) | PDF | HTML | 英語版 (Rev.B) | PDF | HTML | 2025/05/08 |
設計と開発
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5-8-LOGIC-EVM — 5 ~ 8 ピンの DCK、DCT、DCU、DRL、DBV の各パッケージをサポートする汎用ロジックの評価基板 (EVM)
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| VSSOP (DCU) | 8 | Ultra Librarian |