DS92CK16
- Master/Slave Clock Selection in a Backplane Application
- 125 MHz Operation (Typical)
- 100 ps Duty Cycle Distortion (Typical)
- 50 ps Channel to Channel Skew (Typical)
- 3.3V Power Supply Design
- Glitch-free Power on at CLKI/O Pins
- Low Power Design (20 mA @ 3.3V Static)
- Accepts Small Swing (300 mV Typical) Differential Signal Levels
- Industrial Temperature Operating Range (-40°C to +85°C)
- Available in 24-pin TSSOP Packaging
All trademarks are the property of their respective owners.
The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low power dissipation, low noise, and high data rates. The BLVDS side is a transceiver with a separate channel acting as a return/source clock.
The DS92CK16 accepts LVDS (300 mV typical) differential input levels, and translates them to 3V CMOS output levels. An output enable pin OE , when high, forces all CLKOUT pins high.
The device can be used as a source synchronous driver. The selection of the source driving is controlled by the CrdCLKIN and DE pins. This device can be the master clock, driving the inputs of other clock I/O pins in a multipoint environment. Easy master/slave clock selection is achieved along a backplane.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver datasheet (Rev. C) | 2013年 4月 13日 | |
| Application note | High Speed BUS LVDS Clock Distri Using DS92CK16 Clock Distri (Rev. B) | 2013年 4月 26日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。
在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 24 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點