SN65LVEP11

現行

PECL/ECL 1:2 扇出緩衝器

立即訂購

產品規格表

document-pdfAcrobat 2.5V/3.3V PECL/ECL 1:2 Fanout Buffer datasheet (Rev. A) (英文)

SN65LVEP11

現行

產品規格表

立即訂購

產品詳細資料

Function

Translator

Protocols

ECL, PECL

Number of transmitters

2

Number of receivers

1

Signaling rate (Mbps)

6000

Input signal

ECL, PECL

Output signal

ECL, PECL

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Function

Translator

Protocols

ECL, PECL

Number of transmitters

2

Number of receivers

1

Signaling rate (Mbps)

6000

Input signal

ECL, PECL

Output signal

ECL, PECL

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOIC (D)

8

29.4 mm² (4.9 mm × 6 mm)

VSSOP (DGK)

8

14.7 mm² (3 mm × 4.9 mm)

1:2 PECL/ECL Fanout Buffer
Operating Range
- PECL: V_CC = 2.375 V to 3.8V With V_EE = 0 V
- NECL: V_CC = 0 V With V_EE = -2.375V to
  -3.8 V
Open Input Default State
Support for Clock Frequencies > 3.0 GHz
240 ps Typical Propagation Delay
Deterministic Output Value for Open Input Conditions
Q Output Will Default Low When Input Open or at V_EE
Built-in Temperature Compensation
Drop in Compatible to MC10LVEP11, MC100LVEP11
LVDS Input Compatible

1:2 PECL/ECL Fanout Buffer
Operating Range
- PECL: V_CC = 2.375 V to 3.8V With V_EE = 0 V
- NECL: V_CC = 0 V With V_EE = -2.375V to
  -3.8 V
Open Input Default State
Support for Clock Frequencies > 3.0 GHz
240 ps Typical Propagation Delay
Deterministic Output Value for Open Input Conditions
Q Output Will Default Low When Input Open or at V_EE
Built-in Temperature Compensation
Drop in Compatible to MC10LVEP11, MC100LVEP11
LVDS Input Compatible

The SN65LVEP11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain known logic levels when the inputs are in an open condition. Single-ended clock input operation is limited to V_CC ≥ 3 V in PECL mode, or V_EE ≤ 3 V in NECL mode. The device is housed in an industry-standard SOIC-8 package and is also available in TSSOP-8 package option.

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