首頁 介面 LVDS、M-LVDS 和 PECL IC
首頁
介面
LVDS、M-LVDS 和 PECL IC

TB5R3

最後一次購買

四路 PECL 接收器

立即訂購
產品規格表

TB5R3

最後一次購買
產品規格表 立即訂購

產品詳細資料

Function Receiver Protocols PECL Number of transmitters 0 Number of receivers 4 Supply voltage (V) 5 Signaling rate (Mbps) 100 Input signal PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver Protocols PECL Number of transmitters 0 Number of receivers 4 Supply voltage (V) 5 Signaling rate (Mbps) 100 Input signal PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 16 106.09 mm² 10.3 x 10.3
  • Functional Replacement for the Agere BRF1A
  • Pin Equivalent to General Trade 26LS32
  • High Input Impedance Approximately 8 k
  • <2.6-ns Maximum Propagation Delay
  • TB5R3 Provides 50-mV Hysteresis (Typical)
  • -1.1-V to 7.1-V Common-Mode Input Voltage Range
  • Single 5-V ±10% Supply
  • ESD Protection HBM > 3 kV and CDM > 2 kV
  • Operating Temperature Range: -40°C to 85°C
  • Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package
  • APPLICATIONS
    • Digital Data or Clock Transmission Over Balanced Lines
  • Functional Replacement for the Agere BRF1A
  • Pin Equivalent to General Trade 26LS32
  • High Input Impedance Approximately 8 k
  • <2.6-ns Maximum Propagation Delay
  • TB5R3 Provides 50-mV Hysteresis (Typical)
  • -1.1-V to 7.1-V Common-Mode Input Voltage Range
  • Single 5-V ±10% Supply
  • ESD Protection HBM > 3 kV and CDM > 2 kV
  • Operating Temperature Range: -40°C to 85°C
  • Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package
  • APPLICATIONS
    • Digital Data or Clock Transmission Over Balanced Lines

These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels.

The TB5R3 is a pin- and function-compatible replacement for the Agere systems BRF1A; it includes 3-kV HBM and 2-kV CDM ESD protection.

The power-down loading characteristics of the receiver input circuit are approximately 8 k relative to the power supplies; hence they do not load the transmission line when the circuit is powered down.

The packaging for this differential line receiver is a 16-pin gull wing SOIC (DW) or a 16 pin SOIC (D).

The enable inputs of this device include internal pull-up resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.

Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits.

These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels.

The TB5R3 is a pin- and function-compatible replacement for the Agere systems BRF1A; it includes 3-kV HBM and 2-kV CDM ESD protection.

The power-down loading characteristics of the receiver input circuit are approximately 8 k relative to the power supplies; hence they do not load the transmission line when the circuit is powered down.

The packaging for this differential line receiver is a 16-pin gull wing SOIC (DW) or a 16 pin SOIC (D).

The enable inputs of this device include internal pull-up resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.

Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits.
filter 尋找其它 LVDS、M-LVDS 和 PECL IC
下載

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet Quad Differential PECL Receivers datasheet (Rev. A) 2007年 10月 23日

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點