TB5R3
- Functional Replacement for the Agere BRF1A
- Pin Equivalent to General Trade 26LS32
- High Input Impedance Approximately 8 k
- <2.6-ns Maximum Propagation Delay
- TB5R3 Provides 50-mV Hysteresis (Typical)
- -1.1-V to 7.1-V Common-Mode Input Voltage Range
- Single 5-V ±10% Supply
- ESD Protection HBM > 3 kV and CDM > 2 kV
- Operating Temperature Range: -40°C to 85°C
- Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package
- APPLICATIONS
- Digital Data or Clock Transmission Over Balanced Lines
These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels.
The TB5R3 is a pin- and function-compatible replacement for the Agere systems BRF1A; it includes 3-kV HBM and 2-kV CDM ESD protection.
The power-down loading characteristics of the receiver input circuit are approximately 8 k relative to the power supplies; hence they do not load the transmission line when the circuit is powered down.
The packaging for this differential line receiver is a 16-pin gull wing SOIC (DW) or a 16 pin SOIC (D).
The enable inputs of this device include internal pull-up resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited.
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data transmission driver devices are measured with the following output load circuits.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Quad Differential PECL Receivers datasheet (Rev. A) | 2007年 10月 23日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
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| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOIC (DW) | 16 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點