產品詳細資料

Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 BW at Acl (MHz) 36 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 10 Iq per channel (typ) (mA) 0.25 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.4 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 26 2nd harmonic (dBc) 129 3rd harmonic (dBc) 138 Frequency of harmonic distortion measurement (MHz) 0.001 GBW (typ) (MHz) 27 Input bias current (max) (pA) 250000 Features Shutdown CMRR (typ) (dB) 116 Rating Catalog
Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 2.5 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 5.5 BW at Acl (MHz) 36 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 220 Architecture Bipolar, Fully Differential ADC Driver Vn at flatband (typ) (nV√Hz) 10 Iq per channel (typ) (mA) 0.25 Rail-to-rail In to V-, Out Vos (offset voltage at 25°C) (max) (mV) 0.4 Operating temperature range (°C) -40 to 125 Iout (typ) (mA) 26 2nd harmonic (dBc) 129 3rd harmonic (dBc) 138 Frequency of harmonic distortion measurement (MHz) 0.001 GBW (typ) (MHz) 27 Input bias current (max) (pA) 250000 Features Shutdown CMRR (typ) (dB) 116 Rating Catalog
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9 WQFN (RUN) 10 4 mm² 2 x 2
  • Ultra Low-Power:
    • Voltage: 2.5 V to 5.5 V
    • Current: 250 µA
    • Power-Down Mode: 0.5 µA (Typical)
  • Fully Differential Architecture
  • Bandwidth: 36 MHz (Av = 1 V/V)
  • Slew Rate: 200 V/µs
  • THD: –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ)
  • Input Voltage Noise: 10 nV/√Hz (f = 1 kHz)
  • High DC Accuracy:
    • VOS: ±100 µV
    • VOS Drift: ±3 µV/˚C (–40°C to +125°C)
    • AOL: 114 dB
  • Rail-to-Rail Output (RRO)
  • Negative Rail Input (NRI)
  • Output Common-Mode Control
  • 8-Pin SOIC (D) and VSSOP (DGK)
  • 10-Pin WQFN (RUN)
  • Ultra Low-Power:
    • Voltage: 2.5 V to 5.5 V
    • Current: 250 µA
    • Power-Down Mode: 0.5 µA (Typical)
  • Fully Differential Architecture
  • Bandwidth: 36 MHz (Av = 1 V/V)
  • Slew Rate: 200 V/µs
  • THD: –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ)
  • Input Voltage Noise: 10 nV/√Hz (f = 1 kHz)
  • High DC Accuracy:
    • VOS: ±100 µV
    • VOS Drift: ±3 µV/˚C (–40°C to +125°C)
    • AOL: 114 dB
  • Rail-to-Rail Output (RRO)
  • Negative Rail Input (NRI)
  • Output Common-Mode Control
  • 8-Pin SOIC (D) and VSSOP (DGK)
  • 10-Pin WQFN (RUN)

The THS4531A device is a low-power, fully differential amplifier with input common-mode range below the negative rail and rail-to-rail output. The device is designed for low-power data acquisition systems and high-density applications where power consumption and dissipation is critical.

The device features accurate output common-mode control that allows for DC coupling when driving analog-to-digital converters (ADCs). This control, coupled with the input common-mode range below the negative rail and rail-to-rail output, allows for easy interface from single-ended ground-referenced signal sources to successive-approximation registers (SARs), and delta-sigma (ΔΣ) ADCs using only single-supply 2.5-V to 5-V power. The THS4531A is also a valuable tool for general-purpose, low-power differential signal conditioning applications.

The THS4531A device is a low-power, fully differential amplifier with input common-mode range below the negative rail and rail-to-rail output. The device is designed for low-power data acquisition systems and high-density applications where power consumption and dissipation is critical.

The device features accurate output common-mode control that allows for DC coupling when driving analog-to-digital converters (ADCs). This control, coupled with the input common-mode range below the negative rail and rail-to-rail output, allows for easy interface from single-ended ground-referenced signal sources to successive-approximation registers (SARs), and delta-sigma (ΔΣ) ADCs using only single-supply 2.5-V to 5-V power. The THS4531A is also a valuable tool for general-purpose, low-power differential signal conditioning applications.

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重要文件 類型 標題 格式選項 日期
* Data sheet THS4531A Ultra Low-Power, Rail-to-Rail Output, Fully Differential Amplifier datasheet (Rev. D) PDF | HTML 2020年 3月 4日
Application brief Why Use an FDA to Drive an ADC? PDF | HTML 2026年 1月 8日
Application brief Active Filter Design for Differential ADCs (Rev. A) PDF | HTML 2025年 10月 8日
Product overview High Speed Amplifiers for Motor Encoders and Position Sensing PDF | HTML 2025年 4月 11日
Product overview Pairing ADC Drivers With Fully-Differential Input ADCs for Wide Bandwidth Data Acquisition 2024年 4月 1日
Application brief Maximizing System Total Harmonic Distortion Using High Speed Amplifiers 2018年 6月 20日
E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017年 3月 28日
Application note Fully-Differential Amplifiers (Rev. E) 2016年 9月 19日
Analog Design Journal Using fully differential op amps as attenuators, Part 3 2009年 10月 4日
Analog Design Journal Using fully differential op amps as attenuators, Part 2 2009年 7月 14日
Analog Design Journal Using fully differential op amps as attenuators, Part 1 2009年 5月 1日
Analog Design Journal Analysis of fully differential amplifiers 2005年 3月 11日
Analog Design Journal Designing for low distortion with high-speed op amps 2005年 3月 2日
Application note Noise Analysis for High Speed Op Amps (Rev. A) 2005年 1月 17日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

THS4531ADGKEVM — THS4531ADGKEVM 評估模組

The THS4531ADGKEVM is designed to quickly and easily demonstrate the functionality and versatility of the amplifier. The EVM is ready to connect to power, signal source, and test instruments through the use of on-board connectors. The default amplifier configuration is single-ended input, (...)

使用指南: PDF
TI.com 無法提供
模擬型號

THS4531 TINA-TI Reference Design

SLOM262.TSC (3751 KB) - TINA-TI Reference Design
模擬型號

THS4531A PSpice Model (Rev. A)

SLOM350A.ZIP (277 KB) - PSpice Model
模擬型號

THS4531A TINA-TI Reference Design (Rev. A)

SLOM352A.TSC (68 KB) - TINA-TI Reference Design
模擬型號

THS4531A TINA-TI Spice Model (Rev. A)

SLOM351A.ZIP (15 KB) - TINA-TI Spice Model
物料清單

THS4531ADGK EVM Design Files

SLOR110.ZIP (315 KB)
計算工具

SBOR022 TI FDA Calculator

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一,涵蓋我們的類比和電源產品組合,以及特定類比行為模型,且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前,建立完整的終端設備設計和解決方案原型,進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中,您可以搜尋 TI (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
參考設計

TIDA-00176 — 具高解析度位置內插法的正弦/餘弦編碼器介面參考設計

TIDA-00176 參考設計為符合 EMC 規範的 Sin/Cos 位置編碼器工業介面。應用包括需要準確速度和位置控制的工業驅動器。
此設計採用 16 位元雙取樣 ADC,並提供直接投入相容的 14 或 12 位元版本,可最佳化性能與成本。TIDA-00176 也提供使用 SPI 和 QEP 介面輕鬆連接外部處理器的功能,並允許使用選用的嵌入式 ADC。為快速評估,提供 Piccolo F28069M MCU LaunchPad 的範例韌體,可透過 MCU 的 USB 虛擬 COM 埠輸出 Sin/Cos 編碼器的測量角度,解析度高達 28 位元。
Design guide: PDF
電路圖: PDF
參考設計

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The TIDA-00178 reference design is an EMC compliant industrial interface to Sin/Cos position encoders. Applications include industrial drives, which require accurate speed and position control.

The design utilizes a 16-bit dual sample ADC with drop-in compatible 14- or 12-bit versions available, (...)

Design guide: PDF
電路圖: PDF
參考設計

TIDA-00202 — HIPERFACE 位置編碼器介面參考設計

TIDA-00202 參考設計為 HIPERFACE 位置編碼器實作符合 EMC 規範的工業混合型類比和數位介面。具 IEC-ESD 和 IEC-EFT 保護的 3.3V 電源 RS485 收發器用於雙向參數通道。針對類比正弦/餘弦訊號通道,我們提供兩個選項,以便靈活地連接到帶或不帶嵌入式 ADC 的處理器,或者同時使用這兩個選項來實現備援。第一個選項採用具 SPI 輸出的全差動雙 12 位元 ADC,第二個選項採用具有單端類比輸出 (0-3.3V) 的雙差動輸入。此設計採用符合工業規範的 24V 輸入,且電壓範圍廣泛,從 16V 至 36V 均可覆蓋。編碼器的電源供應可設定在 7 至 (...)
Design guide: PDF
電路圖: PDF
參考設計

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This reference design provides interfacing current output Hall sensors and current transformers to differential ADC (standalone and integrated into MCU). The differential signal conditioning circuit is designed to measure motor current with an accuracy of ±0.5% across operating (...)
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電路圖: PDF
參考設計

TIDA-00187 — 延伸全差分放大器的軌至軌輸出範圍,以納入真正的零伏特

Operational amplifiers (op amps) have been used for decades in signal conditioning circuits and measurement systems. An op amp that has an output spanning from negative to positive supply rail are generally referred to as rail-to-rail output (RRO) op amps. These devices have been used increasingly (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (D) 8 Ultra Librarian
VSSOP (DGK) 8 Ultra Librarian
WQFN (RUN) 10 Ultra Librarian

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  • 認證摘要
  • 進行中的可靠性監測
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