TL16C754C
- ST16C654/654D Pin Compatible With Additional Enhancements
- Support up to:
- 24-MHz Crystal Input Clock (1.5 Mbps)
- 48-MHz Oscillator Input Clock (3 Mbps) for 5-V Operation
- 32-MHz Oscillator Input Clock (2 Mbps) for 3.3-V Operation
- 24-MHz Input Clock (1.5 Mbps) for 2.5-V Operation
- 16-MHz Input Clock (1 Mbps) for 1.8-V Operation
- 64-Byte Transmit FIFO
- 64-Byte Receive FIFO With Error Flags
- Programmable and Selectable Transmit and Receive FIFO Trigger
Levels for DMA and Interrupt Generation - Programmable Receive FIFO Trigger Levels for Software/Hardware
Flow Control - Software/Hardware Flow Control
- Programmable Xon/Xoff Characters
- Programmable Auto-RTS and Auto-CTS
- Optional Data Flow Resume by Xon Any Character
- RS-485 Mode Support
- Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
- Characterized for Operation From –40°C to 85°C,
Available in Commercial and Industrial Temperature Grades - Software-Selectable Baud-Rate Generator
- Prescaler Provides Additional Divide-by-4 Function
- Programmable Sleep Mode
- Programmable Serial Interface Characteristics
- 5-, 6-, 7-, or 8-Bit Characters
- Even, Odd, or No Parity Bit Generation and Detection
- 1-, 1.5-, or 2-Stop Bit Generation
- False Start Bit Detection
- Complete Status Reporting Capabilities in Both Normal and Sleep Mode
- Line Break Generation and Detection
- Internal Test and Loopback Capabilities
- Fully Prioritized Interrupt System Controls
- Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)
- Infrared Data Association (IrDA) Capability
The ’754C is a quad universal asynchronous receiver transmitter (UART) with 64-byte FIFOs, automatic hardware and software flow control, and data rates up to 3 Mbps. It incorporates the functionality of four UARTs, each UART having its own register set and FIFOs. The four UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is Asynchronous Communications Element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that four such devices are incorporated into the ’754C. The ’754C offers enhanced features. It has a transmission control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.
Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and software flow control and hardware flow control capabilities.
The ’754C is available in a 64-pin TQFP PM package. RXRDY and TXRDY functionality is not supported in the TL16C754CPM device.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | TL16CP754C, TL16C754C - Quad UARTs With 64-Byte FIFO datasheet (Rev. H) | 2014/1/10 | |||
| * | 勘誤表 | Short STOP Bit Errata (Rev. A) | 2010/10/8 | |||
| Product overview | UART Quick Reference Card (Rev. D) | 2008/4/9 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| LQFP (PM) | 64 | Ultra Librarian |
訂購與品質
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