TMDS361

The TMDS361 is a three-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to three DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth.

The TMDS361 provides an adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps (see Figure 15).

When any of the input ports are selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.

The TMDS361 is designed to be controlled via a local I²C interface or GPIO interface based on the status of the I2C_SEL pin. The local I²C interface in TMDS361 is a slave-only I²C interface. (See the I2C INTERFACE NOTES section.)

I²C Mode: When the I2C_SEL pin is set low, the device is in I²C mode. With local I²C, the interface port status can be read and the advanced configurations of the device such as TMDS output edge rate control, DDC I²C buffer output-voltage-select (OVS) settings (See the DDC 12C FUNCTION DESCRIPTION for detailed description on DDC I²C buffer description and OVS description), device power management, TMDS clock-detect feature and TMDS input-port selection can be set. See Table 8 through Table 11.

GPIO mode: When the I2C_SEL pin is set high, the device is in GPIO control mode. The port selection is controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set, and the default DDC I²C buffer OVS setting (OVS3) is set. See Table 8 and the DDC 12C FUNCTION DESCRIPTION for detailed description of the DDC I²C buffer.

Following are some of the key features (advantages) that TMDS361 provides to the overall sink-side system (HDTV).

• 3×1 switch that supports TMDS data rates up to 3 Gbps on all three input ports.
• ESD: Built-in support for high ESD protection (up to 10 kV on the HDMI source side). The HDMI source-side pins on the TMDS361 are connected via the HDMI/DVI exterior connectors and cable to the HDMI/DVI sources (e.g., DVD player). In TV applications, it can be expected that the source side may be subjected to higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver.
• Adaptive equalization: The built-in adaptive equalization support compensates for intersymbol interference [ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Adaptive equalization adjusts the equalization gain automatically, based on the cable length and the incoming TMDS data rate.
• TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures that the TMDS output port is turned on only if there is a valid TMDS input signal. TMDS clock-detect feature can be by-passed in I²C Mode, See Table 10 and Table 11. It is recommended to enable TMDS clock-detect circuitry during normal operation. However, for HDMI compliance testing (TMDS Termination Voltage Test), the clock detect feature should be disabled by using the I2C mode control. If the customer requires to pass TMDS Termination Voltage Test in GPIO mode with default TMDS clock-detect circuitry enabled, then a valid TMDS clock should be provided for this complaince test, so that the terminations on the TMDS data pair can be connected and thus customer can pass the TMDS Termination Voltage Test.
• DDC I²C buffer: This feature provides isolation on the source side and sink side DDC I²C capacitance, thus helping the sink system to pass system-level compliance.
• Robust TMDS receive stage: This feature ensures that the TMDS361 can work with TMDS input signals having common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI specifications.
• VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS swing of the TMDS361 (if needed) based on the system requirements.
• GPIO or local I²C interface to control the device features.
• TMDS output edge-rate control: This feature adjusts the TMDS361 TMDS output rise and fall times. There are four settings of the rise and fall times that can be chosen. The default setting is the fastest rise and fall time; the other three settings are slower. Slower edge transitions can potentially help the sink system (HDTV) in passing regulatory EMI compliance.